Multi-channel memory system including error correction decoder architecture with efficient area utilization

• US 8,713,417 B2
• Filed: 08/27/2008
• Issued: 04/29/2014
• Est. Priority Date: 08/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jo, Namphil
• Primary Examiner(s): Leibovich, Yair
• Application Number:
  US12/198,992
• Publication Number:
  US 20090063934A1
• Time in Patent Office: 2,071 Days
• Field of Search: 714/785, 714/764, 714/799
• US Class Current: 714/785
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Claims

1. A memory system, comprising:

first and second memory devices; and

a memory controller configured during a read operation to read encoded data stored in both of the first and second memory devices via respective first and second communication channels, wherein the first communication channel communicates a first data set of the encoded data from the first memory device to the memory controller in parallel with the second communication channel communicating a second data set of the encoded data from the second memory device to the memory controller, the memory controller comprising;

a first error detector dedicated to the first communication channel and configured to generate first values indicating first errors in the first data set, and a second error detector dedicated to the second communication channel and configured to generate second values indicating second errors in the second data set in parallel with the generation of the first values;

a multiplexer that selects between the first and second values to generate multiplexed error detection information; and

an error corrector configured to correct the first and second errors in the first and second data sets in response to the multiplexed error detection information.

2. The memory system of claim 1, wherein the memory controller further comprises:

a first buffer that stores the first data set received from the first communication channel; and

a second buffer that stores the second data set received from the second communication channel,

wherein the error corrector comprises an error location identifier that determines respective error locations for the first and second errors in the first and second data sets using the multiplexed error detection information.

3. The memory system of claim 2, wherein the error location identifier simultaneously determines the respective error locations for the first and second errors in the first and second data sets.

4. The memory system of claim 2, wherein the memory controller further comprises:

a third buffer that stores a third data set received from the first communication channel subsequent to the first data set; and

a fourth buffer that stores a fourth data set received from the second communication channel subsequent to the second data set,

wherein the first error detector generates third values indicating third errors in the third data set and the second error detector generates fourth values indicating fourth errors in the fourth data set in parallel with the generation of the third values,

the multiplexer is further configured to multiplex the third and fourth values to generate the multiplexed error detection information,

the error corrector is further configured to correct the third and fourth errors in the third and fourth data sets in response to the multiplexed error detection information, and

the error location identifier determines the respective error locations for the first and second errors in the first and second data sets while the first and second error detectors respectively generate the third and fourth values.

5. The memory system of claim 4, wherein the memory controller further comprises:

a demultiplexer that demultiplexes multiplexed error location identification information provided by the error location identifier.

6. The memory system of claim 1, wherein the error corrector comprises:

an error location identifier that determines respective error locations for the first and second errors in the first and second data sets using the multiplexed error detection information and comprises;

a key equation solver;

a Chien-search algorithm block; and

an error evaluator.

7. The memory system of claim 6, wherein the memory controller further comprises:

a first buffer that stores the first data set received from the first communication channel;

a second buffer that stores the second data set received from the second communication channel;

a third buffer that stores a third data set of the encoded data received from the first communication channel subsequent to the first data set;

a fourth buffer that stores a fourth data set of the encoded data received from the second communication channel subsequent to the second data set,

the first error detector generates third values indicating third errors in the third data set, and the second error detector generates fourth values indicating fourth errors in the fourth data set in parallel with the generation of the third values,

the multiplexer is further configured to multiplex the third and fourth values to generate the multiplexed error detection information, and

the error corrector determines the second errors in the second data set while a corrected first data set is being transmitted to a host device, and while the third data set is being stored in the third buffer, and the fourth data set is being stored in the fourth buffer.

8. The memory system of claim 1, wherein the first error detector calculates first branch metrics of a first data set, and the second error detector calculates second branch metrics of a second data set.

9. The memory system of claim 8, wherein the memory controller further comprises a multiplexer that multiplexes the first and second branch metrics to provide multiplexed first and second branch metrics to the error corrector.

10. The memory system of claim 8, wherein the error corrector comprises:

an add-compare-select block;

a state metrics memory; and

a survivor path memory.

11. A memory system, comprising:

a memory controller having a first input port for communication with a first memory device via a first communication channel, a second input port for communication with a second memory device via a second communication channel, and an error decoder that is receives multiplexed decoding data collectively received from the first and the second communication channels, wherein the error decoder is a convolutional decoder and comprises;

a first branch metrics calculator that calculate first branch metrics for a first data set data received via the first communication channel;

a second branch metrics calculator that calculate second branch metrics for a second data set received via the second communication channel;

an error corrector that corrects first and second errors respectively in the first and second data sets; and

a multiplexer having first and second inputs respectively connected to outputs of the first and second branch metrics calculators, and having an output connected to an input of the error corrector,

wherein the error decoder comprises first and second error detectors respectively dedicated to the first and second communication channels, the first error detector detecting the first errors while the second error detector detects the second errors.

12. A method of processing data received in a memory controller from first and second memory devices, the method comprising:

receiving in the memory controller a first data set from the first memory device via a dedicated first communication channel, a second data set from the second memory device via a dedicated second communication channel in parallel with receiving the first data set, a third data set from the first memory device via the first communication channel subsequent to the first data set, and a fourth data set from the second memory device via the second communication channel subsequent to the second data set and in parallel with receiving the third data set;

detecting first errors in the first data set using a first error detector dedicated to the first communication channel and generating corresponding first values, while at the same time detecting second errors in the second data set using a second error detector dedicated to the second communication channel and generating corresponding second values;

selecting between the first and second values respectively provided to a multiplexer by the first and second detectors;

correcting the first errors in the first data set in an error corrector using the first values passed by the multiplexer, and then subsequently correcting the second errors in the second data set in the error corrector using the second values passed by the multiplexer; and

detecting third errors in the third data set while detecting fourth errors in the fourth data set, while also correcting the first errors in the first data set.

13. The method of claim 12, further comprising identifying locations for the first errors in the first data set prior to correcting the first errors, and identifying locations for the second errors in the second data set prior to correcting the second errors.

14. The method of claim 12, wherein correcting the first errors in the first data set comprises:

solving a key equation for the first data set;

executing a Chien-search algorithm for the first data set; and

evaluating errors in the first data set.

15. The method of claim 12, wherein detecting the respective first and second errors in the first and second data sets comprises calculating respective first and second branch metrics for the first and second data sets.

16. An error decoder used in a memory controller to correct errors in encoded data read from first and second memory devices during a read operation, the error decoder comprising:

a first error detector that receives a first data set of the encoded data from the first memory device via a dedicated first communication channel;

a second error detector that receives a second data set of the encoded data from the second memory device via a dedicated second communication channel in parallel with the first error detector receiving the first data set, wherein the first error detector generates first values indicating first errors in the first data set in parallel with the second error detector generating second values indicating second errors in the second data set;

a multiplexer that selects between the first and second values to generate multiplexed error detection information; and

an error corrector configured to sequentially correct the first errors in the first data set using the multiplexed error detection information, and then the second errors in the second data set using the multiplexed error detection information.

17. The error decoder of claim 16, further comprising:

a first buffer that stores the first data set received from the first communication channel; and

a second buffer that stores the second data set received from the second communication channel,

wherein the error corrector comprises an error location identifier that determines respective error locations for the first and second errors in the first and second data sets using the multiplexed error detection information.

18. The error decoder of claim 17, wherein the error location identifier simultaneously determines first and second error locations respectively located within the first and second data sets.

19. The error decoder of claim 17, further comprising:

a third buffer that stores a third data set received from the first communication channel subsequent to the first data set; and

a fourth buffer that stores a fourth data set received from the second communication channel subsequent to the second data set,

wherein the first error detector generates third values indicating third errors in the third data set and the second error detector generates fourth values indicating fourth errors in the fourth data set in parallel with the generation of the third values,

the multiplexer further selects between the third and fourth values to generate the multiplexed error detection information,

the error corrector is further configured to correct the third and fourth errors in the third and fourth data sets in response to the multiplexed error detection information, and

the error location identifier determines the respective error locations for the first and second errors in the first and second data sets while the first and second error detectors respectively generate the third and fourth values.

20. The error decoder of claim 19, further comprising a demultiplexer that demultiplexes error location identification information provided by the error location identifier.

21. The error decoder of claim 17, wherein the error location identifier comprises:

a key equation solver;

a Chien-search algorithm block; and

an error evaluator.

22. The error decoder of claim 21, further comprising

a third buffer that stores a third data set of the encoded data received from the first communication channel subsequent to the first data set;

a fourth buffer that stores a fourth data set of the encoded data received from the second communication channel subsequent to the second data set,

the first error detector generates third values indicating third errors in the third data set, and the second error detector generates fourth values indicating fourth errors in the fourth data set in parallel with the generation of the third values,

the multiplexer selects between the third and fourth values to generate the multiplexed error detection information, and

the error corrector determines the second errors in the second data set while a corrected first data set is being transmitted to a host device, and while the third data set is being stored in the third buffer, and the fourth data set is being stored in the fourth buffer.

23. The error decoder of claim 16, wherein the first error detector calculates first branch metrics for the first data set, and the second error detector calculates second branch metrics for the second data set.

24. The error decoder of claim 23, further comprising a multiplexer that selects between the first and second branch metrics to provide a selected one of the first and second branch metrics to the error corrector.

25. The error decoder of claim 23, wherein the error corrector comprises:

an add-compare-select block;

a state metrics memory; and

a survivor path memory.