Aware manufacturing of integrated circuits

• US 8,713,484 B2
• Filed: 03/24/2010
• Issued: 04/29/2014
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US12/731,118
• Publication Number:
  US 20100180247A1
• Time in Patent Office: 1,497 Days
• Field of Search: 716 51- 56, 430/5, 430/311
• US Class Current: 716/51
• CPC Class Codes: G03F 7/70091 Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G05B 2219/35028 Adapt design as function of manufacturing merits, features, for manufacturing, DFM
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Claims

1. A non-transitory computer readable medium storing a computer program that when executed by at least one processor performs a design aware process to manufacture an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

receiving an IC design comprising a plurality of wiring layers, each wiring layer comprising a plurality of routes;

identifying dimensional attributes of the plurality of routes of a particular wiring layer by identifying (i) a first width of a first set of routes along a first direction and (ii) a second width of a second set of routes along a second direction for the particular wiring layer, wherein the first direction is different from the second direction and the first width is narrower than the second width;

specifying a manufacturing configuration comprising a specified dipole lens, wherein the dipole lens comprises two poles aligned orthogonal to the first direction; and

manufacturing the IC based on the manufacturing configuration.

2. The non-transitory computer readable medium of claim 1, wherein the dimensional attributes of the plurality of routes comprise at least one of a size, width, rotation, orientation, spacing, density, distance, and pitch of the routes in the particular wiring layer of the IC design.

3. The non-transitory computer readable medium of claim 1, wherein the particular wiring layer is a first wiring layer, the program further comprising a set of instructions for identifying dimensional attributes of a plurality of routes of a second wiring layer, wherein the dimensional attributes of the plurality of routes on the second wiring layer are different from the dimensional attributes of the plurality of routes on the first wiring layer.

4. The non-transitory computer readable medium of claim 1, wherein the first direction is a vertical direction, wherein the dipole lens comprises two poles that are horizontally aligned.

5. The non-transitory computer readable medium of claim 1, wherein the first direction is a vertical direction.

6. The non-transitory computer readable medium of claim 1, wherein the first direction is a 45 degree direction.

7. The non-transitory computer readable medium of claim 1, wherein the particular wiring layer is a first wiring layer and the specified dipole lens is a first dipole lens, wherein the manufacturing configuration further comprises a specified second dipole lens for a second wiring layer of the IC design, wherein the first dipole lens comprises two poles that are vertically aligned and the second dipole lens comprises two poles that are horizontally aligned.

8. A system comprising:

a processor for executing sets of instructions; and

a memory for storing a computer program for performing a design aware process to manufacture an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

receiving an IC design comprising a plurality of wiring layers, each wiring layer comprising a plurality of routes;

identifying (i) a first width of a first set of routes on a first wiring layer and (ii) a second width of a second set of routes on a second wiring layer, wherein the first width is narrower than the second width;

specifying a manufacturing configuration comprising (i) a first set of manufacturing settings for a set of lithographic machines to manufacture the first wiring layer based on the first width of the first set of routes of the first wiring layer and (ii) a second set of manufacturing settings for the set of lithographic machines to manufacture the second wiring layer based on the second width of the second set of routes of the second wiring layer; and

manufacturing the IC based on the manufacturing configuration.

9. The system of claim 8, wherein the first set of routes are aligned in a first direction and the second set of routes are aligned in a second direction.

10. The system of claim 8, wherein the first set of manufacturing settings specify a first light wavelength for the first wiring layer of the IC design and the second set of manufacturing settings specify a second light wavelength for the second wiring layer of the IC design, wherein the first specified light wavelength is shorter than the second specified light wavelength.

11. The system of claim 8, wherein the first set of manufacturing settings specify a first aperture mask for the first wiring layer of the IC design and the second set of manufacturing settings specify a second aperture mask for the second wiring layer of the IC design, wherein the first specified aperture mask provides a larger aperture setting than the second specified aperture mask.

12. The system of claim 8, wherein the first set of manufacturing settings specify a vertically aligned stepper lens when the first set of routes of the first wiring layer require production along a horizontal direction with more precision than along a vertical direction.

13. The system of claim 8, wherein the first set of manufacturing settings specify a horizontally aligned stepper lens when the first set of routes of the first wiring layer require production of IC components along a vertical direction with more precision than along a horizontal direction.

14. A non-transitory computer readable medium storing a computer program that when executed by at least one processor performs a design aware process to manufacture an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

receiving an IC design comprising a plurality of wiring layers, each wiring layer comprising a plurality of routes;

identifying (i) a first width of a first set of routes on a first wiring layer and (ii) a second width of a second set of routes on a second wiring layer, wherein the first width is narrower than the second width;

specifying a manufacturing configuration comprising (i) a first set of manufacturing settings for a set of lithographic machines to manufacture the first wiring layer based on the first width of the first set of routes of the first wiring layer and (ii) a second set of manufacturing settings for the set of lithographic machines to manufacture the second wiring layer based on the second width of the second set of routes of the second wiring layer; and

manufacturing the IC based on the manufacturing configuration.

15. The non-transitory computer readable medium of claim 14, wherein the first set of routes are aligned in a first direction and the second set of routes are aligned in a second direction.

16. The non-transitory computer readable medium of claim 14, wherein the first set of manufacturing settings specify a first light wavelength for the first wiring layer of the IC design and the second set of manufacturing settings specify a second light wavelength for the second wiring layer of the IC design, wherein the first specified light wavelength is shorter than the second specified light wavelength.

17. The non-transitory computer readable medium of claim 14, wherein the first set of manufacturing settings specify a first aperture mask for the first wiring layer of the IC design and the second set of manufacturing settings specify a second aperture mask for the second wiring layer of the IC design, wherein the first specified aperture mask provides a larger aperture setting than the second specified aperture mask.

18. The non-transitory computer readable medium of claim 14, wherein the first set of manufacturing settings specify a vertically aligned stepper lens when the first set of routes of the first wiring layer require production along a horizontal direction with more precision than along a vertical direction.

19. The non-transitory computer readable medium of claim 14, wherein the first set of manufacturing settings specify a horizontally aligned stepper lens when the first set of routes of the first wiring layer require production of IC components along a vertical direction with more precision than along a horizontal direction.