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Tools and methods for yield-aware semiconductor manufacturing process target generation

  • US 8,713,511 B1
  • Filed: 09/17/2012
  • Issued: 04/29/2014
  • Est. Priority Date: 09/16/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit fabricated in a preselected fabrication process, the integrated circuit designed using a computer-implemented method including the steps of:

  • a) characterizing, by a computer, the yield of a predetermined circuit for each one of a set of operating conditions, the predetermined circuit implemented in a first semiconductor manufacturing process;

    b) providing a transistor-level circuit description of the predetermined circuit, the transistor-level description suitable for porting;

    c) porting the transistor-level circuit description of the predetermined circuit to provide a ported circuit simulation model;

    d) providing a set of circuit simulation parameter values;

    e) selecting, using, a factorial design of experiments, a subset of the circuit simulation parameter values;

    f) running the circuit simulation using the selected subset of the circuit simulation parameter values;

    g) comparing at least one output of the circuit simulation to at least one pass/fail criterion; and

    h) recording the result of the comparing step;

    wherein characterizing the yield comprises operating each one of a plurality of the predetermined circuits over a set of values within a predetermined range for at least one operating condition, and recording whether the predetermined circuit satisfies a predetermined performance constraint at each one of the set of values for the at least one operating condition.

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