Tools and methods for yield-aware semiconductor manufacturing process target generation
First Claim
1. An integrated circuit fabricated in a preselected fabrication process, the integrated circuit designed using a computer-implemented method including the steps of:
- a) characterizing, by a computer, the yield of a predetermined circuit for each one of a set of operating conditions, the predetermined circuit implemented in a first semiconductor manufacturing process;
b) providing a transistor-level circuit description of the predetermined circuit, the transistor-level description suitable for porting;
c) porting the transistor-level circuit description of the predetermined circuit to provide a ported circuit simulation model;
d) providing a set of circuit simulation parameter values;
e) selecting, using, a factorial design of experiments, a subset of the circuit simulation parameter values;
f) running the circuit simulation using the selected subset of the circuit simulation parameter values;
g) comparing at least one output of the circuit simulation to at least one pass/fail criterion; and
h) recording the result of the comparing step;
wherein characterizing the yield comprises operating each one of a plurality of the predetermined circuits over a set of values within a predetermined range for at least one operating condition, and recording whether the predetermined circuit satisfies a predetermined performance constraint at each one of the set of values for the at least one operating condition.
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Accused Products
Abstract
An integrated circuit having at least one array of circuit cells, each circuit cell having a plurality of transistors each performing a specified function, the transistors having predefined performance parameter margins for the specified function, the circuit cells designed by providing at least one operating condition for the circuit cell; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, which is defined by a semiconductor process that results in transistors having such transistor characteristics; providing an array of instances based upon the value of the sigma and using a design of experiments factorial calculation; providing a metric of interest by which to deter-nine pass/fail instances; extracting individual pass/fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.
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Citations
20 Claims
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1. An integrated circuit fabricated in a preselected fabrication process, the integrated circuit designed using a computer-implemented method including the steps of:
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a) characterizing, by a computer, the yield of a predetermined circuit for each one of a set of operating conditions, the predetermined circuit implemented in a first semiconductor manufacturing process; b) providing a transistor-level circuit description of the predetermined circuit, the transistor-level description suitable for porting; c) porting the transistor-level circuit description of the predetermined circuit to provide a ported circuit simulation model; d) providing a set of circuit simulation parameter values; e) selecting, using, a factorial design of experiments, a subset of the circuit simulation parameter values; f) running the circuit simulation using the selected subset of the circuit simulation parameter values; g) comparing at least one output of the circuit simulation to at least one pass/fail criterion; and h) recording the result of the comparing step; wherein characterizing the yield comprises operating each one of a plurality of the predetermined circuits over a set of values within a predetermined range for at least one operating condition, and recording whether the predetermined circuit satisfies a predetermined performance constraint at each one of the set of values for the at least one operating condition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit having at least one array of circuit cells, each circuit cell in the circuit cell array designed using a plurality of transistors each of which performs a specified function, the transistors each having a predefined performance parameter margin for the specified function, the circuit cells designed according to a computer implemented method including the steps of:
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providing at least one targeted operating condition for the bit cell array; providing, using a factorial design of experiments, a value of circuit level sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic; providing an array of instances based upon the value of the circuit level sigma; providing a metric of interest by which to determine pass and failure instances; extracting individual pass and fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A computer program product including a non-transitory computer-readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations for designing a circuit cell, the instructions comprising:
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providing at least one targeted operating condition for the bit cell array; providing a factorial design of experiments a value of circuit level sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic; providing an array of instances based upon the value of the circuit level sigma; providing a metric of interest by which to determine pass and failure instances; extracting individual pass and fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.
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Specification