Tools and methods for yield-aware semiconductor manufacturing process target generation

• US 8,713,511 B1
• Filed: 09/17/2012
• Issued: 04/29/2014
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., Leshner, Samuel
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/621,698
• Time in Patent Office: 589 Days
• Field of Search: 716/134, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit having at least one array of circuit cells, each circuit cell having a plurality of transistors each performing a specified function, the transistors having predefined performance parameter margins for the specified function, the circuit cells designed by providing at least one operating condition for the circuit cell; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, which is defined by a semiconductor process that results in transistors having such transistor characteristics; providing an array of instances based upon the value of the sigma and using a design of experiments factorial calculation; providing a metric of interest by which to deter-nine pass/fail instances; extracting individual pass/fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.

Claims

1. An integrated circuit fabricated in a preselected fabrication process, the integrated circuit designed using a computer-implemented method including the steps of:

a) characterizing, by a computer, the yield of a predetermined circuit for each one of a set of operating conditions, the predetermined circuit implemented in a first semiconductor manufacturing process;

b) providing a transistor-level circuit description of the predetermined circuit, the transistor-level description suitable for porting;

c) porting the transistor-level circuit description of the predetermined circuit to provide a ported circuit simulation model;

d) providing a set of circuit simulation parameter values;

e) selecting, using, a factorial design of experiments, a subset of the circuit simulation parameter values;

f) running the circuit simulation using the selected subset of the circuit simulation parameter values;

g) comparing at least one output of the circuit simulation to at least one pass/fail criterion; and

h) recording the result of the comparing step;

wherein characterizing the yield comprises operating each one of a plurality of the predetermined circuits over a set of values within a predetermined range for at least one operating condition, and recording whether the predetermined circuit satisfies a predetermined performance constraint at each one of the set of values for the at least one operating condition.

2. The integrated circuit of claim 1, wherein operating each one of a plurality of predetermined circuits comprises coupling each one of the plurality of predetermined circuits to a tester, providing, by the tester, power to each of the circuits, providing, by the tester, driving waveforms, and measuring at least one output of the predetermined circuit.

3. The integrated circuit of claim 1, wherein the predetermined circuit is a logic circuit.

4. The integrated circuit of claim 1, wherein the predetermined circuit is as standard cell.

5. The integrated circuit of claim 1, wherein the predetermined circuit is a memory bit cell.

6. The integrated circuit of claim 1, wherein the predetermined circuit is an SRAM bit cell.

7. The integrated circuit of claim 1, wherein the predetermined circuit performs an analog function.

8. The integrated circuit of claim 1, wherein the set of operating conditions includes V_DDmin.

9. The integrated circuit of claim 1, the design of the integrated circuit further comprising the steps of;

selecting a different subset of simulation parameter values from the set of simulation parameter values; and

repeating steps (f), (g) and (h).

10. The integrated circuit of claim 5, wherein the at least one pass/fail criterion is selected from the group consisting of static noise margin, write margin, read current, retention state noise margin and writeability.

11. The integrated circuit of claim 5, wherein the at least one pass/fail criterion is selected from the group consisting of active power dissipation, leakage power dissipation and propagation delay.

12. An integrated circuit having at least one array of circuit cells, each circuit cell in the circuit cell array designed using a plurality of transistors each of which performs a specified function, the transistors each having a predefined performance parameter margin for the specified function, the circuit cells designed according to a computer implemented method including the steps of:

providing at least one targeted operating condition for the bit cell array;

providing, using a factorial design of experiments, a value of circuit level sigma over a predefined range;

determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic;

providing an array of instances based upon the value of the circuit level sigma;

providing a metric of interest by which to determine pass and failure instances;

extracting individual pass and fail instances for the metric of interest; and

determining a yield for the array of circuit cells for the targeted operating condition.

13. The integrated circuit of claim 12, wherein the array of circuit cells is an array of SRAM bit cells.

14. The integrated circuit of claim 13, wherein said metric of interest is selected from a group consisting of read static noise margin, write margin, read current, write delay, retention state noise margin, and leakage power.

15. The integrated circuit of claim 12, wherein the at least one variable transistor characteristics includes transistor threshold voltage.

16. The integrated circuit of claim 12, wherein said metric of interest is selected from a group consisting of active power dissipation, leakage power dissipation and propagation delay.

17. The integrated circuit of claim 12, wherein the plurality of transistors includes at least one DDC transistor.

18. The integrated circuit of claim 12, wherein the circuit cell design further includes the steps of:

simulating a circuit across a plurality of circuit level sigma values, wherein the device variations are chosen by the aggregate of the constituent devices; and

using multiple simulation runs with each permutation of each device having positive, zero, or negative variation, wherein the multiple simulations encompass all permutations of the devices at the specified circuit level sigma.

19. The method of claim 18, wherein the plurality of circuit level sigma values are chosen from the low probability tail of the circuit level distribution.

20. A computer program product including a non-transitory computer-readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations for designing a circuit cell, the instructions comprising:

providing at least one targeted operating condition for the bit cell array;

providing a factorial design of experiments a value of circuit level sigma over a predefined range;

determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic;

providing an array of instances based upon the value of the circuit level sigma;

providing a metric of interest by which to determine pass and failure instances;

extracting individual pass and fail instances for the metric of interest; and

determining a yield for the array of circuit cells for the targeted operating condition.