Photoelectric conversion device and method for operating the same

• US 8,716,646 B2
• Filed: 10/04/2011
• Issued: 05/06/2014
• Est. Priority Date: 10/08/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hirose, Atsushi
• Primary Examiner(s): LUU, THANH X
• Application Number:
  US13/252,226
• Publication Number:
  US 20120085892A1
• Time in Patent Office: 945 Days
• Field of Search: 250/214.R, 250/214.A
• US Class Current: 250/214.R
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 31/02019 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence

Abstract

In a photoelectric conversion device including a photodiode and a current mirror circuit, a diode-connected transistor is provided in parallel with the photodiode. The transistor serves as a leakage path for rapidly discharging charge stored in the gate capacitance in the current mirror circuit. Thus, the response speed of the photoelectric conversion device is increased, and output of an abnormal value is reduced.

Claims

1. A photoelectric conversion device comprising:

a photodiode;

a first transistor;

a plurality of second transistors; and

a third transistor,

wherein an anode of the photodiode is electrically connected to a drain electrode and a gate electrode of the first transistor, and gate electrodes of the plurality of second transistors,

wherein a cathode of the photodiode and drain electrodes of the plurality of second transistors are electrically connected to a first terminal,

wherein a source electrode of the first transistor and source electrodes of the plurality of second transistors are electrically connected to a second terminal,

wherein the third transistor is a diode-connected transistor, and

wherein the third transistor is electrically connected in parallel with the photodiode.

2. The photoelectric conversion device according to claim 1, wherein the first terminal is electrically connected to a circuit configured to select a high power supply potential and a ground potential, and the second terminal is electrically connected to a wiring supplying a low power supply potential.

3. The photoelectric conversion device according to claim 1, wherein the first to third transistors are n-channel transistors.

4. The photoelectric conversion device according to claim 1, wherein the third transistor comprises an oxide semiconductor.

5. The photoelectric conversion device according to claim 1, wherein a gate width of the third transistor is larger than a gate width of the first transistor.

6. The photoelectric conversion device according to claim 1, wherein a gate length of the third transistor is smaller than a gate length of the first transistor.

7. A photoelectric conversion device comprising:

a photodiode;

a first transistor;

a plurality of second transistors; and

a third transistor,

wherein an anode of the photodiode is electrically connected to a drain electrode and a gate electrode of the first transistor, gate electrodes of the plurality of second transistors, and a drain electrode and a gate electrode of the third transistor,

wherein a cathode of the photodiode, drain electrodes of the plurality of second transistors, and a source electrode of the third transistor are electrically connected to a first terminal,

wherein a source electrode of the first transistor and source electrodes of the plurality of second transistors are electrically connected to a second terminal,

wherein the third transistor is a diode-connected transistor, and

wherein the third transistor is electrically connected in parallel with the photodiode.

8. The photoelectric conversion device according to claim 7, wherein the first terminal is electrically connected to a circuit configured to select a high power supply potential and a ground potential, and the second terminal is electrically connected to a wiring supplying a low power supply potential.

9. The photoelectric conversion device according to claim 7, wherein the first to third transistors are n-channel transistors.

10. The photoelectric conversion device according to claim 7, wherein the third transistor comprises an oxide semiconductor.

11. The photoelectric conversion device according to claim 7, wherein a gate width of the third transistor is larger than a gate width of the first transistor.

12. The photoelectric conversion device according to claim 7, wherein a gate length of the third transistor is smaller than a gate length of the first transistor.

13. A photoelectric conversion device comprising:

a photodiode;

a first transistor;

a plurality of second transistors; and

a third transistor,

wherein a cathode of the photodiode is electrically connected to a drain electrode and a gate electrode of the first transistor, and gate electrodes of the plurality of second transistors,

wherein a source electrode of the first transistor and source electrodes of the plurality of second transistors are electrically connected to a first terminal,

wherein an anode of the photodiode and drain electrodes of the plurality of second transistors are electrically connected to a second terminal,

wherein the third transistor is a diode-connected transistor, and

wherein the third transistor is electrically connected in parallel with the photodiode.

14. The photoelectric conversion device according to claim 13, wherein the first terminal is electrically connected to a circuit configured to select a high power supply potential and a ground potential, and the second terminal is electrically connected to a wiring supplying a low power supply potential.

15. The photoelectric conversion device according to claim 13, wherein the first to third transistors are p-channel transistors.

16. The photoelectric conversion device according to claim 13, wherein the third transistor comprises an oxide semiconductor.

17. The photoelectric conversion device according to claim 13, wherein a gate width of the third transistor is larger than a gate width of the first transistor.

18. The photoelectric conversion device according to claim 13, wherein a gate length of the third transistor is smaller than a gate length of the first transistor.

19. A photoelectric conversion device comprising:

a photodiode;

a first transistor;

a plurality of second transistors; and

a third transistor,

wherein a cathode of the photodiode is electrically connected to a drain electrode and a gate electrode of the first transistor, gate electrodes of the plurality of second transistors, and a source electrode of the third transistor,

wherein a source electrode of the first transistor, source electrodes of the plurality of second transistors, and a drain electrode and a gate electrode of the third transistor are electrically connected to a first terminal,

wherein an anode of the photodiode and drain electrodes of the plurality of second transistors are electrically connected to a second terminal,

wherein the third transistor is a diode-connected transistor, and

wherein the third transistor is electrically connected in parallel with the photodiode.

20. The photoelectric conversion device according to claim 19, wherein the first terminal is electrically connected to a circuit configured to select a high power supply potential and a ground potential, and the second terminal is electrically connected to a wiring supplying a low power supply potential.

21. The photoelectric conversion device according to claim 19, wherein the third transistor comprises an oxide semiconductor.

22. The photoelectric conversion device according to claim 19, wherein a gate width of the third transistor is larger than a gate width of the first transistor.

23. The photoelectric conversion device according to claim 19, wherein a gate length of the third transistor is smaller than a gate length of the first transistor.