Contact structure of semiconductor device

• US 8,716,765 B2
• Filed: 03/23/2012
• Issued: 05/06/2014
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/428,972
• Publication Number:
  US 20130248927A1
• Time in Patent Office: 774 Days
• Field of Search: 257192-194, 257/288, 438197-199, 438/230, 438299-300, 438/429, 438/478, 438/595, 438/607
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/28506 of conductive layers
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm.

Claims

1. A contact structure for a semiconductor device comprising:

a substrate comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and the strained material extends upward over the major surface of the substrate;

a first metal layer over the strained material;

a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and

a second metal layer over the dielectric layer.

2. The contact structure of claim 1, wherein the strained material comprises SiGe, SiC, or SiP.

3. The contact structure of claim 1, wherein the first metal layer comprises TiN or TaN.

4. The contact structure of claim 1, wherein the dielectric layer comprises TiO₂.

5. The contact structure of claim 1, wherein the dielectric layer comprises Al₂O₃, NiO, or HfO₂.

6. The contact structure of claim 1, wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.

7. The contact structure of claim 1, wherein the second metal layer comprises Al, Ni, NiPt, or Pt.

8. A metal oxide semiconductor field effect transistor (MOSFET) comprising:

a substrate comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a gate stack on the major surface of the substrate;

a shallow trench isolations (STI) region within the substrate, the cavity being between the STI region and the gate stack; and

a contact structure at least partially in the cavity, wherein the contact structure comprises;

a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and the strained material extends upward over the major surface of the substrate;

a first metal layer over the strained material;

a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and

a second metal layer over the dielectric layer.

9. The MOSFET of claim 8, wherein the strained material comprises SiGe, SiC, or Sip.

10. The MOSFET of claim 8, wherein the first metal layer comprises TiN or TaN.

11. The MOSFET of claim 8, wherein the dielectric layer comprises TiO₂.

12. The MOSFET of claim 8, wherein the dielectric layer comprises Al₂O₃, NiO, or HfO₂.

13. The MOSFET of claim 8, wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.

14. The MOSFET of claim 8, wherein the second metal layer comprises Al, Ni, NiPt, or Pt.

15. A transistor, comprising:

a fin structure comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a gate stack on the major surface of the fin structure; and

a contact structure comprising;

an epitaxially grown strained material in the cavity, wherein the strained material extends upward beyond the major surface,

a first metal layer over the strained material completely covering an upper surface of the strained material;

a dielectric layer over the first metal layer; and

a second metal layer over the dielectric layer.

16. The transistor of claim 15, wherein the strained material comprises SiGe, SiC, or SiP.

17. The transistor of claim 16, wherein

the first metal layer comprises TiN or TaN, and

the second metal layer comprises Al, Ni, NiPt, or Pt.

18. The transistor of claim 17, wherein the dielectric layer comprises TiO₂, Al₂O₃, NiO, or HfO₂.

19. The transistor of claim 15, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm.

20. The transistor of claim 15, wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.