Semiconductor device having a buried gate type MOS transistor and method of manufacturing same

• US 8,716,774 B2
• Filed: 05/24/2012
• Issued: 05/06/2014
• Est. Priority Date: 05/27/2011
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Inventors: Mikasa, Noriaki
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/479,810
• Publication Number:
  US 20120299073A1
• Time in Patent Office: 712 Days
• Field of Search: 257/296, 257/331, 257/E27.017, 257/E29.262
• US Class Current: 257/296
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of having a first gate groove having first and second sides opposite to each other;

a first diffusion region in the semiconductor substrate underneath the first gate groove;

a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and

a third diffusion region in the semiconductor substrate, the third diffusion region covering the second side of the first gate groove, the third diffusion region being continuous to the first diffusion region and separated from the second diffusion region so that a lower portion of the first side of the first gate groove serves as a first channel region, the third diffusion region having a bottom which is deeper than a bottom of the first gate groove, and the bottom of the third diffusion region being different in level from the bottom of the first diffusion region,

wherein each of the semiconductor substrate and the first channel region is of a first conductivity type and each of the first, second, and third diffusion regions is of a second conductivity type so that each of the first and third diffusion regions forms a PN junction with the semiconductor substrate and each of the second diffusion region and first diffusion region forms a PN junction with the first channel region.

2. The semiconductor device according to claim 1, wherein the bottom of the first diffusion region is deeper than the bottom of the third diffusion region.

3. The semiconductor device according to claim 1, wherein the bottom of the first diffusion region is shallower than the bottom of the third diffusion region.

4. The semiconductor device according to claim 1, wherein the first diffusion region includes a first side diffusion portion which extends along a lower portion of the first side of the first groove, the first side diffusion portion is separate from the second diffusion region.

5. The semiconductor device according to claim 1, further comprising:

a first gate insulator covering inside walls of the first gate groove;

a first gate electrode in a lower portion of the first gate groove and on the first gate insulator; and

a first buried insulator filling an upper portion of the first gate groove, and being positioned over the first gate electrode.

6. The semiconductor device according to claim 1, wherein the semiconductor substrate has a second gate groove having third and fourth sides opposite to each other, and

the third diffusion region is disposed between the first and second gate grooves.

7. The semiconductor device according to claim 6, further comprising:

a fourth diffusion region in the semiconductor substrate underneath the second gate groove; and

a fifth diffusion region in the semiconductor substrate, the fifth diffusion region covering an upper portion of the fourth side of the second gate groove,

wherein the third diffusion region covers the third side of the second gate groove, the third diffusion region is continuous to the fourth diffusion region and separated from the fifth diffusion region so that a lower portion of the fourth side of the second gate groove serves as a second channel region, the bottom of the third diffusion region is deeper than a bottom of the second gate groove, the bottom of the third diffusion region is different in level from a bottom of the fourth diffusion region and each of the semiconductor substrate and the second channel region is of a first conductivity type and each of the third, fourth and fifth diffusion regions is of a second conductivity type so that each of the fourth and third diffusion regions forms a PN junction with the semiconductor substrate and each of the fifth diffusion region and fourth diffusion region forms a PN junction with the second channel region.

8. The semiconductor device according to claim 7, wherein the bottom of the fourth diffusion region is deeper than the bottom of the third diffusion region.

9. The semiconductor device according to claim 7, wherein the bottom of the fourth diffusion region is shallower than the bottom of the third diffusion region.

10. The semiconductor device according to claim 7, wherein the fourth diffusion region includes a second side diffusion portion which extends along a lower portion of the fourth side of the second gate groove, the second side diffusion portion is separate from the fifth diffusion region.

11. The semiconductor device according to claim 6, further comprising:

a second gate insulator covering inside surfaces of the second gate groove;

a second gate electrode in a lower portion of the second gate groove and on the second gate insulator; and

a second buried insulator filling an upper portion of the second gate groove and being positioned over the second gate electrode.

12. The semiconductor device according to claim 1, further comprising:

a plurality of first isolation regions in the semiconductor substrate, each of the first isolation region extending to a first direction, at least two first isolation regions defining an active region so that the active region is disposed between the first isolation regions; and

a plurality of second isolation regions in the semiconductor substrate, each of the second isolation region extending to the second direction intersecting the first direction, at least two second isolation regions defining a device formation region of the active region so that the device formation region is disposed between the second isolation regions.

13. The semiconductor device according to claim 12, wherein bottoms of the first and third diffusion regions are shallower than bottoms of the first and second isolation regions.

14. The semiconductor device according to claim 12, wherein the first and second isolation regions comprise an insulator filling first and second isolation grooves in the semiconductor substrate.

15. The semiconductor device according to claim 12, wherein the first and second isolation regions comprise:

an insulator filing a first isolation groove and partially filling a lower portion of a second isolation groove;

an insulating layer covering inside walls of an upper portions of the second isolation groove; and

a conductor being formed in an upper portion of the second isolation groove with the insulating layer therebetween.

16. The semiconductor device according to claim 1, further comprising:

a bit line coupled to the third diffusion region;

a contact plug coupled to the second diffusion region; and

a capacitor coupled to the contact plug.

17. A semiconductor device comprising:

a semiconductor substrate of having a first gate groove having first and second sides opposite to each other;

a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of the first side of the first gate groove; and

a second diffusion region in the semiconductor substrate, the second diffusion region continuously extending from an upper portion of the second side to a bottom of the first side to cover at least the second side and a bottom of the first gate groove, the second diffusion region being separated from the first diffusion region so that a lower portion of the first side of the first gate groove serves as a first channel region,

wherein each of the semiconductor substrate and the first channel region is of a first conductivity type and each of the first and second diffusion regions is of a second conductivity type so that the second diffusion regions forms a PN junction with the semiconductor substrate and each of the first diffusion region and second diffusion region forms a PN junction with the first channel region.

18. The semiconductor device according to claim 17, wherein the second diffusion region includes a first side diffusion portion which extends along a lower portion of the first side of the first gate groove, the first side diffusion portion is separate from the first diffusion region.

19. The semiconductor device according to claim 18, further comprising:

a second gate groove having third and fourth sides opposite to each other; and

a third diffusion region in the semiconductor substrate, the third diffusion region covering an upper portion of the fourth side of the second gate groove,

wherein the second diffusion region is disposed between the first and second gate grooves, the second diffusion region continuously extends from an upper portion of the third side to a bottom of the fourth side to cover at least the third side and a bottom of the second gate groove, the second diffusion region is separated from the third diffusion region so that a lower portion of the fourth side of the second gate groove serves as a second channel region, and each of the semiconductor substrate and the second channel region is of a first conductivity type and each of the second and third diffusion regions is of a second conductivity type so that each of the third diffusion region and second diffusion region forms a PN junction with the second channel region.

20. The semiconductor device according to claim 19, wherein the second diffusion region includes a second side diffusion portion which extends along a lower portion of the fourth side of the second gate groove, and the second side diffusion portion is separate from the third diffusion region.