Semiconductor device having a buried gate type MOS transistor and method of manufacturing same
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate of having a first gate groove having first and second sides opposite to each other;
a first diffusion region in the semiconductor substrate underneath the first gate groove;
a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and
a third diffusion region in the semiconductor substrate, the third diffusion region covering the second side of the first gate groove, the third diffusion region being continuous to the first diffusion region and separated from the second diffusion region so that a lower portion of the first side of the first gate groove serves as a first channel region, the third diffusion region having a bottom which is deeper than a bottom of the first gate groove, and the bottom of the third diffusion region being different in level from the bottom of the first diffusion region,wherein each of the semiconductor substrate and the first channel region is of a first conductivity type and each of the first, second, and third diffusion regions is of a second conductivity type so that each of the first and third diffusion regions forms a PN junction with the semiconductor substrate and each of the second diffusion region and first diffusion region forms a PN junction with the first channel region.
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Abstract
A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate of having a first gate groove having first and second sides opposite to each other; a first diffusion region in the semiconductor substrate underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate, the third diffusion region covering the second side of the first gate groove, the third diffusion region being continuous to the first diffusion region and separated from the second diffusion region so that a lower portion of the first side of the first gate groove serves as a first channel region, the third diffusion region having a bottom which is deeper than a bottom of the first gate groove, and the bottom of the third diffusion region being different in level from the bottom of the first diffusion region, wherein each of the semiconductor substrate and the first channel region is of a first conductivity type and each of the first, second, and third diffusion regions is of a second conductivity type so that each of the first and third diffusion regions forms a PN junction with the semiconductor substrate and each of the second diffusion region and first diffusion region forms a PN junction with the first channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor device comprising:
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a semiconductor substrate of having a first gate groove having first and second sides opposite to each other; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of the first side of the first gate groove; and a second diffusion region in the semiconductor substrate, the second diffusion region continuously extending from an upper portion of the second side to a bottom of the first side to cover at least the second side and a bottom of the first gate groove, the second diffusion region being separated from the first diffusion region so that a lower portion of the first side of the first gate groove serves as a first channel region, wherein each of the semiconductor substrate and the first channel region is of a first conductivity type and each of the first and second diffusion regions is of a second conductivity type so that the second diffusion regions forms a PN junction with the semiconductor substrate and each of the first diffusion region and second diffusion region forms a PN junction with the first channel region. - View Dependent Claims (18, 19, 20)
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Specification