Power device with self-aligned source regions

• US 8,716,783 B2
• Filed: 10/10/2011
• Issued: 05/06/2014
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Herrick, Robert, Losee, Becky, Probst, Dean
• Primary Examiner(s): Tran, Long K
• Application Number:
  US13/270,050
• Publication Number:
  US 20120119291A1
• Time in Patent Office: 939 Days
• Field of Search: 257/302, 257/330, 257/331, 257/332, 257/905, 257/E27.091, 257/E29.201, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.

Claims

1. A field effect transistor (FET), comprising:

a trench extending into a silicon layer, the trench having an upper sidewall that fans out;

a contact opening extending into the silicon layer adjacent the trench such that the trench and the contact opening form a common upper sidewall portion;

a body region adjacent the trench; and

a source region extending in the body region, the source region having a conductivity type opposite that of the body region, the source region being self-aligned to the trench, a majority of the source region being disposed below the common upper sidewall.

2. The FET of claim 1, further comprising a metal layer extending into the contact opening and contacting a sidewall of the source region.

3. The FET of claim 1, wherein an entirety of the source region is disposed below the common upper sidewall.

4. The FET of claim 1, wherein the common upper sidewall together with a sidewall of the source region define a sidewall of the contact opening.

5. The FET of claim 1, further comprising:

a gate electrode recessed in the trench;

a gate dielectric insulating the gate electrode from the body region; and

a dielectric region extending in the trench over the gate electrode.

6. The FET of claim 5, wherein the dielectric region has at least a portion that is fully contained within the trench, and a sidewall of the at least a portion of the dielectric region together with a sidewall of the source region define a sidewall of the contact opening.

7. The FET of claim 5, wherein the dielectric region has at least a portion that:

(a) is fully contained within the trench, and (b) defines an upper portion of a sidewall of the contact opening.

8. The FET of claim 5, wherein the dielectric region has a portion that:

(a) is fully contained within the trench, and (b) extends directly over at least a portion of the source region.

9. The FET of claim 1, wherein the contact opening is self-aligned to the trench.

10. A field effect transistor (FET) comprising:

a trench extending through a body region and terminating within an epitaxial layer below the body region, the trench having an upper portion wider than a lower portion of the trench;

a gate electrode disposed in the lower portion of the trench, the upper portion substantially being disposed above a top surface of the gate electrode;

a contact opening extending into the body region adjacent the trench such that the trench and a contact opening adjacent the trench define a common upper sidewall, the common upper sidewall being above an upper surface of the body; and

a source region of a conductivity type extending in the body region adjacent a sidewall of the trench.

11. The FET of claim 10,. further comprising a metal layer extending into the contact opening and contacting a sidewall of the source region.

12. The FET of claim 10, wherein the common upper sidewall together with a sidewall of the source region define a sidewall of the contact opening.

13. The FET of claim 10, wherein the upper portion has a portion that extends directly over at least a portion of the source region.

14. The FET of claim 10, further comprising:

a gate dielectric insulating the gate electrode from the body region; and

a dielectric region extending over the gate electrode.

15. The FET of claim 14,. wherein the dielectric region has at least a portion that is fully contained within the trench, a sidewall of the at least a portion of the dielectric region together with a sidewall of the source region define a sidewall of the contact opening.

16. The FET of claim 10, wherein the gate electrode is recessed in the trench below the upper portion.

17. An apparatus, comprising:

a trench disposed in a silicon layer, the trench having an upper sidewall portion that fans out;

a gate electrode disposed in the trench;

a contact opening defined, at least in part by, the upper sidewall portion, the upper sidewall being disposed substantially above a bottom surface of the contact opening; and

a source region in contact with at least a portion of the upper sidewall portion.

18. The apparatus of claim 17, wherein the upper sidewall portion is disposed directly over at least a portion of the source region.

19. The apparatus of claim 17, wherein the gate electrode has a top surface that is recessed in the trench below the upper sidewall portion.

20. The apparatus of claim 17, further comprising:

a body region adjacent the trench, the source region being disposed in the body region and having a conductivity type opposite a conductivity type of the body region.