Selective floating body SRAM cell

• US 8,716,810 B2
• Filed: 12/14/2012
• Issued: 05/06/2014
• Est. Priority Date: 07/20/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Josephine B., Chang, Leland, Koester, Steven J., Sleight, Jeffrey W.
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US13/714,973
• Publication Number:
  US 20130099316A1
• Time in Patent Office: 508 Days
• Field of Search: 257/350, 257/390, 257/E27.112, 365/185.23, 365/189.11, 365/188.63
• US Class Current: 257/390
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Claims

1. A memory cell comprising:

N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six;

wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor;

wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; and

wherein each of said pull-up transistors comprises a floating body device;

wherein each of the said pull-down transistors comprises at least one body tie that electrically contacts a source or a drain to the body of the pull-down transistor;

wherein each of the said pull-down transistors comprises a pair of Schottky body ties that electrically contacts the body to both the source and the drain.

2. The memory cell of claim 1, wherein each of the said access transistors and each of the said pull-down transistors is an n-type transistor, and each of the said pull-up transistors is a p-type transistor.

3. The memory cell of claim 1, wherein the memory cell comprises a static random access memory cell in which each of the pull-up and pull-down transistors comprise a gate coupled to a channel of at least one of the access transistors.