Selective floating body SRAM cell
First Claim
1. A memory cell comprising:
- N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six;
wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor;
wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; and
wherein each of said pull-up transistors comprises a floating body device;
wherein each of the said pull-down transistors comprises at least one body tie that electrically contacts a source or a drain to the body of the pull-down transistor;
wherein each of the said pull-down transistors comprises a pair of Schottky body ties that electrically contacts the body to both the source and the drain.
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Accused Products
Abstract
A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
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Citations
3 Claims
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1. A memory cell comprising:
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N transistors comprising at least one pair of access transistors, at least one pair of pull-down transistors, and at least one pair of pull-up transistors, said N transistors arranged to form a memory cell, wherein N is an integer at least equal to six; wherein each of the said access transistors and each of the said pull-down transistors is a same one of an n-type or a p-type transistor, and each of the said pull-up transistors is the other of an n-type or a p-type transistor; wherein each of the said access transistors comprises a floating body device and each of the said pull-down transistors comprises a non-floating body device; and wherein each of said pull-up transistors comprises a floating body device;
wherein each of the said pull-down transistors comprises at least one body tie that electrically contacts a source or a drain to the body of the pull-down transistor;
wherein each of the said pull-down transistors comprises a pair of Schottky body ties that electrically contacts the body to both the source and the drain. - View Dependent Claims (2, 3)
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Specification