Magnetoresistive element and method of manufacturing the same

• US 8,716,818 B2
• Filed: 03/23/2012
• Issued: 05/06/2014
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshikawa, Masatoshi, Harakawa, Hideaki, Kishi, Tatsuya, Hosotani, Keiji, Seto, Satoshi, Ozeki, Jyunichi
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US13/428,465
• Publication Number:
  US 20130001652A1
• Time in Patent Office: 774 Days
• Field of Search: 257421-427, 438/3
• US Class Current: 257/421
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

Claims

1. A magnetoresistive element comprising:

a storage layer having a variable and perpendicular magnetization;

a tunnel barrier layer on the storage layer;

a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer;

a hard mask layer on the reference layer;

a side wall spacer layer on side walls of the reference layer and the hard mask layer; and

a boundary layer between the tunnel barrier layer and the reference layer,

wherein an in-plane size of the reference layer is smaller than an in-plane size of the storage layer, a difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less, and the side wall spacer layer comprises a material selected from a group consisting of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

2. The element of claim 1,

wherein the side wall spacer layer includes a stacked structure comprising layers, and an uppermost layer of the stacked structure comprises the material.

3. The element of claim 1,

wherein an in-plane size of the side wall spacer layer is 1 nm or less.

4. The element of claim 1,

wherein the side wall spacer layer includes a re-deposition layer which is formed by patterning of the reference layer.

5. The element of claim 1,

wherein the hard mask layer comprises a material selected from a group consisting of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

6. The element of claim 1,

wherein the side wall spacer layer and the hard mask layer comprises the same material.

7. The element of claim 1,

wherein an in-plane shape of the reference layer is a circular shape.

8. The element of claim 1,

wherein an in-plane shape of the reference layer is an elliptical shape.

9. The element of claim 1,

wherein the tunnel barrier layer comprises MgO.

10. The element of claim 1, further comprising:

a shift adjustment layer between the reference layer and the hard mask layer, the shift adjustment layer which adjusts a shift of a magnetic hysteresis curve of the storage layer.

11. The element of claim 10,

wherein the shift adjustment layer comprises a material selected from a group consisting of Pt, Pd and Ir.

12. The element of claim 1, further comprising:

a protection layer covering the reference layer and the storage layer, the protection layer which protects the reference layer and the storage layer from H₂O and O₂.

13. The element of claim 12,

wherein the protection layer comprises a material selected from a group consisting of SiN, AlN and BN.

14. The element of claim 1,

wherein a magnetization of the storage layer is reversed by a spin-momentum-transfer.

15. A magnetic random access memory comprising:

the element of claim 1;

FET having first and second switch terminals and a control terminal, the first switch terminal connected to one of the storage layer and the reference layer of the element;

a word line connected to the control terminal of the FET;

a first bit line connected to the other one of the storage layer and the reference layer of the element;

a second bit line connected to the second switch terminal of the FET;

a first control circuit controlling a potential of the word line; and

a second control circuit controlling potentials of the first and second bit lines.

16. A magnetoresistive element comprising:

a storage layer having a variable and perpendicular magnetization;

a tunnel barrier layer on the storage layer;

a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer;

a hard mask layer on the reference layer, the hard mask layer comprises a material selected from a group consisting of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN; and

a side wall spacer layer on side walls of the reference layer and the hard mask layer,

wherein an in-plane size of the reference layer is smaller than an in-plane size of the storage layer, a difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less, and the side wall spacer layer comprises a material selected from a group consisting of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

17. The element of claim 16,

wherein the side wall spacer layer includes a stacked structure comprising layers, and an uppermost layer of the stacked structure comprises the material.

18. The element of claim 16,

wherein an in-plane size of the side wall spacer layer is 1 nm or less.

19. The element of claim 16,

wherein the side wall spacer layer includes a re-deposition layer which is formed by patterning of the reference layer.

20. A magnetic random access memory comprising:

the element of claim 16;

FET having first and second switch terminals and a control terminal, the first switch terminal connected to one of the storage layer and the reference layer of the element;

a word line connected to the control terminal of the FET;

a first bit line connected to the other one of the storage layer and the reference layer of the element;

a second bit line connected to the second switch terminal of the FET;

a first control circuit controlling a potential of the word line; and

a second control circuit controlling potentials of the first and second bit lines.