Series-parallel reconfigurable cell voltage equalization circuit designed using MOSFET as switches thereof, and driver circuit thereof

• US 8,716,894 B2
• Filed: 10/27/2011
• Issued: 05/06/2014
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Japan Aerospace Exploration Agency, Japan Capacitor Industrial Co., Ltd.
• Original Assignee: Japan Aerospace Exploration Agency, Japan Capacitor Industrial Co., Ltd.
• Inventors: Uno, Masatoshi, Kukita, Akio, Ito, Kazushige, Sekido, Tsutomu, Nagata, Kaoru, Shoji, Kazuhiro
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Kessie, Daniel
• Application Number:
  US13/283,519
• Publication Number:
  US 20120286578A1
• Time in Patent Office: 922 Days
• Field of Search: 307/77, 307/71, 326/61, 326/62, 315/111.01
• US Class Current: 307/77
• CPC Class Codes: H02J 7/0014 Circuits for equalisation of charge between batteries
• CPC Class Codes: H02J 7/0024 Parallel/serial switching of connection of batteries to charge or load circuit

Abstract

It is an object to provide a circuit for equalizing voltages of energy storage cells, with less number of element and simpler circuit configuration than ever before.

A plurality of field-effect transistors are arranged such that each of a plurality of parallel circuits formed, in one of connection states attained by switching of the switches, by connecting in parallel energy storage cells to perform mutual charging and discharging, includes a field-effect transistor adapted to avoid blocking a current having one of opposite polarities in the each of the plurality of parallel circuits, and a field-effect transistor adapted to avoid blocking a current having the other polarity in the each of the plurality of parallel circuits. This makes it possible to perform a voltage equalization operation using a small number of transistors.

Claims

1. A voltage equalization circuit comprising:

a first series circuit constructed by connecting n energy storage cells in series (wherein n is an integer of 2 or more);

second and third series circuits each constructed by connecting (n−

1) energy storage cells in series; and

first and second switch groups, wherein the voltage equalization circuit is configured to;

when each of a plurality of switches making up the first switch group is turned on, attain a first connection state in which each k-th energy storage cell constituting the first series circuit (wherein k is an integer of 2 to n) is connected in parallel to each (k−

1)-th energy storage cell constituting the second series circuit to form (n−

1) parallel circuits, and each 1-th energy storage cell constituting the first series circuit (wherein l is an integer of 1 to (n−

1)) is connected in parallel to each 1-th energy storage cell constituting the third series circuit to form (n−

1) parallel circuits; and

,

when each of a plurality of switches making up the second switch group is turned on, attain a second connection state in which each 1-th energy storage cell constituting the first series circuit is connected in parallel to each 1-th energy storage cell constituting the second series circuit to form (n−

1) parallel circuits, and each k-th energy storage cell constituting the first series circuit is connected in parallel to each (k−

1)-th energy storage cell constituting the third series circuit to form (n−

1) parallel circuits, the voltage equalization circuit being operable to switch between the first and second connection states to thereby equalize voltages of the energy storage cells making up the first to third series circuits, and wherein;

the first switch group is made up by positioning field-effect transistors as switches in each of the parallel circuits formed in the first connection state, and arranged such that the each of the parallel circuits formed in the first connection state includes a field-effect transistor adapted to avoid blocking a current having one of opposite polarities in the each of the parallel circuits, and a field-effect transistor adapted to avoid blocking a current having the other polarity in the each of the parallel circuits; and

the second switch group is made up by positioning field-effect transistors as switches in each of the parallel circuits formed in the second connection state, and arranged such that the each of the parallel circuits formed in the second connection state includes a field-effect transistor adapted to avoid blocking a current having one of opposite polarities in the each of the parallel circuits, and a field-effect transistor adapted to avoid blocking a current having the other polarity in the each of the parallel circuits.

2. The voltage equalization circuit as defined in claim 1, wherein each of the switches making up the first and second switch groups is a metal-oxide semiconductor field-effect transistor (MOSFET).

3. The voltage equalization circuit as defined in claim 2, wherein:

the first switch group is configured by positioning MOSFETs such that, when one of the energy storage cells making up the first series circuit and one of the energy storage cells making up the second series circuit are connected in parallel in the first connection state to form an energy storage cell pair, MOSFETs thereof are located, respectively, between respective high-potential electrodes of the energy storage cell pair and between respective low-potential electrodes of the energy storage cell pair, in such a manner that a source electrode of each of the MOSFETs is connected to a side of the electrodes of the storage cell comprised in the first series circuit and a drain electrode of each of the MOSFETs is connected to a side of the electrodes of the energy storage cell comprised in the second series circuit, and,

when one of the energy storage cells making up the first series circuit and one of the energy storage cells making up the third series circuit are connected in parallel in the first connection state to form an energy storage cell pair, MOSFETs thereof are located, respectively, between respective high-potential electrodes of the energy storage cell pair and between respective low-potential electrodes of the energy storage cell pair, in such a mariner that a drain electrode of each of the MOSFETs is connected to a side of the electrodes of the storage cell comprised in the first series circuit and a source electrode of each of the MOSFETs is connected to a side of the electrodes of the energy storage cell comprised in the third series circuit; and

the second switch group is configured by positioning MOSFETs such that, when one of the energy storage cells making up the first series circuit and one of the energy storage cells making up the second series circuit are connected in parallel in the second connection state to form an energy storage cell pair, MOSFETs thereof are located, respectively, between respective high-potential electrodes of the energy storage cell pair and between respective low-potential electrodes of the energy storage cell pair, in such a manner that a drain electrode of each of the MOSFETs is connected to a side of the electrodes of the storage cell comprised in the first series circuit and a source electrode of each of the MOSFETs is connected to a side of the electrodes of the energy storage cell comprised in the second series circuit, and, when one of the energy storage cells making up the first series circuit and one of the energy storage cells making up the third series circuit are connected in parallel in the second connection state to form an energy storage cell pair, MOSFETs thereof are located, respectively, between respective high-potential electrodes of the energy storage cell pair and between respective low-potential electrodes of the energy storage cell pair, in such a manner that a source electrode of each of the MOSFETs is connected to a side of the electrodes of the storage cell comprised in the first series circuit and a drain electrode of each of the MOSFETs is connected to a side of the electrodes of the energy storage cell comprised in the third series circuit.

4. The voltage equalization circuit as defined in claim 3, which comprises:

a coupling capacitor connected in series to a gate electrode of each of the MOSFETs making up the first and second switch groups;

a resistor connected between the source electrode and the gate electrode of each of the MOSFETs; and

a diode connected in parallel to the resistor to avoid blocking a current from flowing in a direction from the source electrode to the gate electrode, whereby each of the MOSFETs is switchable between its ON and OFF states according to control of a driving signal to be input into the gate electrode through the coupling capacitor.

5. The voltage equalization circuit as defined in claim 4, wherein a driving signal output circuit comprising:

a light-emitting section having a light-emitting element; and

a light-receiving section provided with a light-receiving element adapted to generate an electric signal in response to light emitting of the light-emitting element and a push-pull circuit adapted to output the driving signal in response to the electric signal, and electrically isolated with respect to the light-emitting element;

is connected to each of the coupling capacitors, and the driving signal output circuit is adapted to control the driving signal to be input into the gate electrode through the coupling capacitor, to thereby switch between ON and OFF states of each of the MOSFETs.

6. The voltage equalization circuit as defined in claim 5, wherein the driving signal output circuit includes:

a first driving signal output circuit connected to all of the coupling capacitors connected in series to respective ones of the gate electrodes of the MOSFETs making up the first switch group, and adapted to output a driving signal to all of the gate electrodes of the MOSFETs making up the first switch group through respective ones of the coupling capacitors; and

a second driving signal output circuit connected to all of the coupling capacitors connected in series to respective ones of the gate electrodes of the MOSFETs making up the second switch group, and adapted to output a driving signal to all of the gate electrodes of the MOSFETs making up the second switch group through respective ones of the coupling capacitors,

wherein each of the first and second driving signal output circuits is adapted to control the driving signal to be input therefrom to thereby switch between the ON and OFF states of each of the MOSFETs making up a respective one of the first and second switch groups.

7. An uninterruptible power supply configured as the voltage equalization circuit as defined in claim 5 or 6, which is configured such that the light-emitting element provided in each of the driving signal output circuits is connected to a light-emitting element driver circuit which is connected to one or more of the energy storage cells making up the first to third series circuits, so as to allow the one or more energy storage cells to be used as a power supply for operating the light-emitting element driver circuit, and the push-pull circuit provided in each of the driving signal output circuits is connected to one or more of the energy storage cells making up the first to third series circuits, so as to allow the one or more energy storage cells to be used as a power supply for operating the push-pull circuit.

8. A voltage equalization circuit constructed by:

connecting in series N modules each provided as the voltage equalization circuit as defined in claim 5 in which the number n is defined as n_i, wherein i is an integer of 1 to N (N being an integer of 2 or more) (each of the N modules will hereinafter be referred to as “

the i-th module”

); and

connecting an energy storage cell to each position between the second series circuits and between the third series circuits in directly-connected two of the N modules, wherein a reference potential point of the push-pull circuit comprised in the driving signal output circuit for switching between the ON and OFF states of each of the MOSFETs comprised in the i-th module is connected to one of the energy storage cells comprised in the i-th module.

9. A voltage equalization circuit constructed by:

alternately connecting, in parallel, (i) m series circuits each of which is constructed by connecting n energy storage cells in series (wherein m is an integer of 1 or more, and n is an integer of 2 or more) and (ii) m or m±

1 and multiple series circuits each of which is constructed by connecting (n−

1) energy storage cells in series (except for cases where the total number of parallel-connected series circuits is (4L−

2), wherein L is a natural number); and

providing first and second switch groups,

wherein the voltage equalization circuit is configured to;

when each of a plurality of switches making up the first switch group is turned on, attain a first connection state in which an individual one of the energy storage cells comprised in each of the series circuits is connected in parallel to one or more of the energy storage cells comprised in the one or more series circuits connected in parallel to the series circuit having the individual energy storage cell, to form a plurality of parallel circuits; and

,

when each of a plurality of switches making up the second switch group is turned on, attain a second connection state in which an individual one of the energy storage cells comprised in each of the series circuits is connected in parallel to one or more of the energy storage cells comprised in the one or more series circuits connected in parallel to the series circuit having the individual energy storage cell, to form a plurality of parallel circuits different from the parallel circuits formed in the first connection state,

so as to equalize voltages of the energy storage cells making up the respective series circuits according to switching between the first and second connection states, and wherein;

the first switch group is made up by positioning field-effect transistors in each of the parallel circuits formed in the first connection state, and arranged such that the each of the parallel circuits formed in the first connection state includes a field-effect transistor adapted to avoid blocking a current having one of opposite polarities in the each of the parallel circuits, and a field-effect transistor adapted to avoid blocking a current having the other polarity in the each of the parallel circuits; and

the second switch group is made up by positioning field-effect transistors in each of the parallel circuits formed in the second connection state, and arranged such that the each of the parallel circuits formed in the second connection state includes a field-effect transistor adapted to avoid blocking a current having one of opposite polarities in the each of the parallel circuits, and a field-effect transistor adapted to avoid blocking a current having the other polarity in the each of the parallel circuits.