Integrated tester chip using die packaging technologies

• US 8,717,057 B2
• Filed: 08/15/2008
• Issued: 05/06/2014
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kaskoun, Kenneth, Jha, Sanjay K.
• Primary Examiner(s): Vazquez, Arleen M
• Assistant Examiner(s): LE, SON T
• Application Number:
  US12/192,719
• Publication Number:
  US 20090322368A1
• Time in Patent Office: 2,090 Days
• Field of Search: 324/763, 32476201-76203, 324/750.3, 324/158.1, 714/733
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized.

Claims

1. An integrated circuit (IC) package comprising:

a plurality of tiers including one or more circuit chips, in which each circuit chip performs a different function;

a plurality of circuits under test included in the one or more circuit chips, at least one of the plurality of circuits under test having logical components on different tiers;

a tester chip on a different tier from the one or more circuit chips, the tester chip consisting of a test circuit operable to test each of the different functions of the one or more circuit chips within the IC package, the tester chip including an external pin for each of the plurality of circuits, through which each circuit of the IC package is tested, the tester chip operable to communicate with the plurality of circuits through vias, the tester chip including a standardized interface to the one or more circuit chips to test the different functions of the one or more circuit chips; and

a memory separate from the tester chip and mounted on one of the plurality of tiers within the IC package, the memory configured to store a program designed to control the test circuit on the tester chip, the test circuit to perform validation testing on the plurality of circuits, the program downloaded to the memory after the memory is positioned in the IC package.

2. A method for testing a stacked integrated circuit (IC) device within an IC package, said method comprising:

positioning a plurality of chips and a tester chip, consisting of a test circuit, on a plurality of tiers of the IC package, each chip operable to perform a different function, the tester chip including an external pin for each of the plurality of chips, through which each circuit of each chip of the stacked IC device is tested, the tester chip positioned on a different tier from the plurality of chips, said positioning comprising electrically coupling said plurality of chips with through vias;

interfacing with the plurality of chips through a standardized interface to test the different functions of the plurality of chips;

providing test instructions to at least one of the plurality of chips and the tester chip, wherein said test instructions are provided to at least one of said plurality of chips and the tester chip prior to said positioning; and

testing with the tester chip, a function of said plurality of chips under control of at least one of said coupled chips by communication through at least some of the through vias.

3. An integrated circuit (IC) package comprising:

at least one circuit constructed on both a first chip in a first tier including a launching latch in a pipeline stage, and a second chip in a second tier including a capturing latch in the pipeline stage, the first chip and the second chip operable to perform different functions associated with the at least one circuit;

a third chip consisting of a test circuit, the third chip including an external pin for each of the first and second chips, through which each circuit of the first chip and the second chip of the IC package is tested, the third chip on a different tier from the first and second chips, the third chip operable to communicate with the first chip and the second chip with a plurality of through vias, said test circuit capable of testing a function of said at least one circuit, as well as a plurality of circuits contained in the IC package, the third chip including a standardized interface to the first chip and the second chip to test different functions of the first chip and the second chip; and

means for wirelessly receiving operational instructions unique to the at least one circuit, the operational instructions used to configure the test circuit, wherein the operational instructions are contained in a memory resident within the IC package.

4. A method for constructing a stacked integrated circuit (IC) device, said method comprising:

selecting a plurality of chips, in which each of the plurality of chips performs a different function, a plurality of circuits under test included in the plurality of chips;

selecting at least one tester chip consisting of a test circuit capable of testing a plurality of coupled combinations of the plurality of circuits of the plurality of chips on tiers different from a tier of the at least one tester chip, the tester chip including a tester pin for each of the plurality of circuits, through which each circuit of the stacked IC device is tested, the tester chip including a standardized interface to each of the plurality of chips to test the plurality of coupled combinations of the plurality of circuits;

stacking said plurality of chips, and said tester chip, such that portions of said plurality of chips become electrically coupled with vias, and so that circuits of the plurality of chips split across tiers become testable, wherein said stacked chips are in the stacked IC device, in which the stacked chips communicate with through vias; and

programming the at least one tester chip to perform testing on the stacked chips, wherein the programming is performed from time to time or prior to said stacking, and wherein the time to time programming is wirelessly communicated to the stacked IC device.

5. An integrated circuit (IC) package comprising:

a plurality of tiers including one or more circuit chips, in which each circuit chip performs a different function;

a plurality of circuits under test included in the one or more circuit chips, at least one of the plurality of circuits under test having logical components on different tiers;

a tester chip consisting of means for testing each of the different functions of the one or more circuit chips within the IC package, the tester chip including an external pin for each of the plurality of circuits, through which each circuit of the IC package is tested, the tester chip disposed on a different tier from the plurality of circuits, the tester chip operable to communicate with the plurality of circuits through vias, the tester chip including a standardized interface to the one or more circuit chips to test the different functions of the one or more circuit chips; and

a memory separate from the tester chip and mounted on one of the plurality of tiers within the IC package, the memory configured to store a program designed to control the testing means on the tester chip, the testing means to perform validation testing on the plurality of circuits, the program downloaded to the memory after the memory is positioned in the IC package.

6. An integrated circuit (IC) package comprising:

at least one circuit constructed on both a first chip in a first tier including a launching latch in a pipeline stage, and a second chip in a second tier including a capturing latch in the pipeline stage, the first chip and the second chip operable to perform different functions associated with the at least one circuit;

a third chip consisting of a means for testing a function of the at least one circuit, the third chip including a tester pin for each of the first and second chips, through which each circuit of the first chip and the second chip of the IC package is tested, the third chip on a different tier from the first and second chips, the third chip operable to communicate with the first chip and the second chip with a plurality of through vias, as well as a plurality of circuits contained in the IC package, the third chip including a standardized interface to the first chip and the second chip to test different functions of the first chip and the second chip; and

means for wirelessly receiving operational instructions unique to the at least one circuit, the operational instructions used to configure the testing means, wherein the operational instructions are contained in a memory resident within the IC package.