High voltage latching and DC restoration isolation and level shifting method and apparatus
First Claim
Patent Images
1. A V-bus circuit, comprising:
- a first level circuit;
a level shifter connected to the first level circuit;
a second level circuit connected to the level shifter; and
a capacitor connected to a terminal of the second level circuit,wherein the level shifter is configured to control inputs of the first and second level circuits wherein the first level circuit comprises;
a port, a first logic gate which can produce a hard high, a second logic gate which can produce a hard low, a third logic gate which can produce a soft high and a fourth logic gate which can produce a soft low, the port being connected to an output of the first, second, third and fourth logic gates.
0 Assignments
0 Petitions
Accused Products
Abstract
A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit, and a latching circuit connected to the capacitor. The latching circuit is powered by a second voltage range and is configured to restore and/or minimize charge loss of the capacitor during a voltage transition at the capacitor. A device and method for analog isolation and measurement configured to measure an analog voltage at a second potential without requiring analog circuits at the second potential.
11 Citations
9 Claims
-
1. A V-bus circuit, comprising:
-
a first level circuit; a level shifter connected to the first level circuit; a second level circuit connected to the level shifter; and a capacitor connected to a terminal of the second level circuit, wherein the level shifter is configured to control inputs of the first and second level circuits wherein the first level circuit comprises; a port, a first logic gate which can produce a hard high, a second logic gate which can produce a hard low, a third logic gate which can produce a soft high and a fourth logic gate which can produce a soft low, the port being connected to an output of the first, second, third and fourth logic gates. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification