Adaptive cascode circuit using MOS transistors

• US 8,717,086 B2
• Filed: 09/05/2013
• Issued: 05/06/2014
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Grimm, Michael, Chen, Jun
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/018,570
• Publication Number:
  US 20140002051A1
• Time in Patent Office: 243 Days
• Field of Search: 327/306, 327/309, 327/325, 327/326, 327/333, 327/419, 327/427, 327/434, 327/436, 330/253
• US Class Current: 327/436
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 5/084 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal

Abstract

The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.

Claims

1. An adaptive cascode circuit, comprising:

a) a main MOS transistor, wherein a source of said main MOS transistor is configured as a first terminal of said adaptive cascode circuit, and wherein a gate of said main MOS transistor is configured as a control terminal of said adaptive cascode circuit;

b) n adaptive MOS transistors coupled in series to a drain of said main MOS transistor, wherein a drain of a first adaptive MOS transistor is configured as a second terminal of said adaptive cascode circuit, and wherein n is an integer greater than one;

c) a shutdown clamping circuit coupled to gates of said n adaptive MOS transistors, wherein said shutdown clamping circuit comprises (n+1) shutdown clamping voltages that are less than corresponding rated drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors, wherein said shutdown clamping circuit is configured to clamp drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors to corresponding said shutdown clamping voltages when said main MOS transistor and said n adaptive MOS transistors are shutdown; and

d) n conduction clamping circuits coupled to gates of corresponding said n adaptive MOS transistors, wherein said n conduction clamping circuits comprise n conduction clamping voltages greater than corresponding conduction threshold voltages of said adaptive MOS transistors, wherein said n conduction clamping circuits are configured to clamp said gate voltages of said n adaptive MOS transistors to corresponding said n conduction clamping voltages when said n adaptive MOS transistors and said main MOS transistor are conducting.

2. The adaptive cascode circuit of claim 1, further comprising:

a) n gate-source clamping circuits coupled between gates and sources of corresponding said n adaptive MOS transistors, wherein said n gate-source clamping circuits comprise n gate-source clamping voltages no larger than rated gate-source voltages of said n adaptive MOS transistors; and

b) wherein when said n adaptive MOS transistors and said main MOS transistor are conducting, said gate-source clamping circuits are configured to clamp gate-source voltages of said n adaptive MOS transistors to corresponding said n gate-source clamping voltages.

3. The adaptive cascode circuit of claim 2, wherein:

a) said n adaptive MOS transistors and main MOS transistor comprise N-type MOS transistors, and each of said n gate-source clamping circuits comprises a first zener diode; and

b) an anode of said first zener diode is coupled to a source of a corresponding said adaptive MOS transistor, and a cathode of said first zener diode is coupled to a gate of a corresponding said adaptive MOS transistor.

4. The adaptive cascode circuit of claim 2, wherein:

a) said n adaptive MOS transistors and said main MOS transistor comprise P-type MOS transistors, each of said n gate-source clamping circuits comprises a second zener diode; and

b) an anode of said second zener diode is coupled to a gate of a corresponding said adaptive MOS transistor, and a cathode of said second zener diode is coupled to a source of a corresponding said adaptive MOS transistor.

5. The adaptive cascode circuit of claim 1, wherein:

a) said n adaptive MOS transistors and said main MOS transistor comprise N-type MOS transistors, a first terminal of said shutdown clamping circuit is coupled to a second terminal of said adaptive cascode circuit, and a second terminal of said shutdown clamping circuit is coupled to ground; and

b) each of said n conduction clamping circuits comprises a first diode, wherein a cathode of said first diode is coupled to a gate of a corresponding said adaptive MOS transistor, and an anode of said first diode is coupled to a voltage source.

6. The adaptive cascode circuit of claim 5, wherein:

a) said shutdown clamping circuit comprises series coupled (n+1) third zener diodes, wherein n common nodes of said (n+1) third zener diodes are respectively coupled to gates of said n adaptive MOS transistors;

b) a cathode of a first of said third zener diodes is configured as a first terminal of said shutdown clamping circuit to couple with a second terminal of said adaptive cascode circuit; and

c) an anode of said n^th of said third zener diodes is configured as a second terminal of said shutdown clamping circuit to couple with ground.

7. The adaptive cascode circuit of claim 6, further comprising a third diode, wherein an anode of said third diode is coupled to a second terminal of said adaptive cascode circuit, and wherein a cathode of said third diode is coupled to a first terminal of said shutdown clamping circuit.

8. The adaptive cascode circuit of claim 1, wherein:

a) said n adaptive MOS transistors and said main MOS transistor comprise P-type MOS transistors, a first terminal of said shutdown clamping circuit is coupled to a highest voltage, and a second terminal of said shutdown clamping circuit is coupled to a second terminal of said adaptive cascode circuit; and

b) each of said n conduction clamping circuits comprises a second diode, wherein an anode of said second diode is coupled to a gate of a corresponding said adaptive MOS transistor, and a cathode of said second diode is coupled to a voltage source with a value of a difference voltage between said highest voltage and a rated gate-source voltage of said main MOS transistor.

9. The adaptive cascode circuit of claim 8, wherein:

a) said shutdown clamping circuit comprises series coupled (n+1) fourth zener diodes, wherein n common nodes of said (n+1) fourth zener diodes are respectively coupled to gates of said n adaptive MOS transistors;

b) an anode of a first of said fourth zener diodes is configured as a second terminal of said shutdown clamping circuit to couple with a second terminal of said adaptive cascode circuit; and

c) a cathode of the (n+1)^th of said fourth zener diodes is configured as a first terminal of said shutdown clamping circuit to couple with the highest voltage.

10. The adaptive cascode circuit of claim 9, further comprising a fourth diode, wherein a cathode of said fourth diode is coupled to a second terminal of said adaptive cascode circuit, and an anode of said fourth diode is coupled to a second terminal of said shutdown clamping circuit.

11. The adaptive cascode circuit of claim 1, wherein:

a) said n adaptive MOS transistors and said main MOS transistor comprise N-type MOS transistors, said n adaptive MOS transistors are coupled to at least one of a plurality of enhanced drivers, wherein each of said enhanced drivers comprises a push-pull circuit and a fifth diode;

b) an input terminal of said push-pull circuit is coupled to a corresponding said conduction clamping circuit, and an output terminal of said push-pull circuit is coupled to a gate of a corresponding said adaptive MOS transistor; and

c) an anode of said fifth diode is coupled to a voltage source, and a cathode of said fifth diode is coupled to a gate of a corresponding said adaptive MOS transistor.

12. The adaptive cascode circuit of claim 1, wherein:

a) said n adaptive MOS transistors and said main MOS transistor comprise P-type MOS transistors, wherein said n adaptive MOS transistors are coupled to at least one of a plurality of enhanced drivers, and wherein each of said enhanced drivers comprises a push-pull circuit and a sixth diode;

b) an input terminal of said push-pull circuit is coupled to a corresponding said conduction clamping circuit, and an output terminal of said push-pull circuit is coupled to a gate of a corresponding said adaptive MOS transistor; and

c) a cathode of said sixth diode is coupled to a voltage source, and an anode of said sixth diode is coupled to a gate of said adaptive MOS transistor.

13. The adaptive cascode circuit of claim 1, wherein said n adaptive MOS transistors are configured to be turned on in sequence after said main MOS transistor is turned on.

14. The adaptive cascode circuit of claim 13, wherein said n conduction clamping circuits are configured to clamp said gate voltages of said n adaptive MOS transistors to corresponding said n conduction clamping voltages after all of said n adaptive MOS transistors are turned on.

15. A switching power supply, comprising:

a) an input supply coupled to a first switch at an input node;

b) a second switch coupled to said first switch at a common node, wherein each of said first and second switches comprises said adaptive cascode circuit of claim 1; and

c) an inductor coupled to said common node and an output node.

16. The switching power supply of claim 15, wherein:

a) said first switch comprises P-type MOS transistors as said adaptive and said main MOS transistors in said adaptive cascode circuit; and

b) said second switch comprises N-type MOS transistors as said adaptive and said main MOS transistors in said adaptive cascode circuit.