System and method for high speed packet transmission
First Claim
1. A system comprising:
- a blade, the blade comprising;
one or more ports for receiving or transmitting packets; and
an integrated circuit, the integrated circuit comprising;
a first core; and
a second core;
wherein the first core comprises a first switching circuit operative to transfer a first packet from the second core to the first core; and
wherein the second core comprises a second switching circuit operative to transfer a second packet from the first core to the second core.
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Accused Products
Abstract
The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.
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Citations
30 Claims
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1. A system comprising:
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a blade, the blade comprising; one or more ports for receiving or transmitting packets; and an integrated circuit, the integrated circuit comprising; a first core; and a second core; wherein the first core comprises a first switching circuit operative to transfer a first packet from the second core to the first core; and wherein the second core comprises a second switching circuit operative to transfer a second packet from the first core to the second core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system comprising:
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a blade, the blade comprising; one or more ports for receiving or transmitting packets; and an integrated circuit, the integrated circuit comprising; a first core; and a second core; wherein the first core comprises a first switching circuit operative to transfer a first packet from the first core to the second core; and wherein the second core comprises a second switching circuit operative to transfer a second packet from the second core to the first core. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method comprising:
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receiving a packet at a first core of an integrated circuit of a blade, the blade comprising the integrated circuit and one or more ports for receiving or transmitting packets, the integrated circuit comprising the first core and a second core; analyzing the packet at the first core to determine whether to transfer the packet to the second core of the integrated circuit; and upon determining to transfer the packet to the second core, storing the packet in a switching circuit located in the second core. - View Dependent Claims (24, 25, 26)
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27. A method comprising:
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receiving a packet at a first core of an integrated circuit of a blade, the blade comprising the integrated circuit and one or more ports for receiving or transmitting packets, the integrated circuit comprising the first core and a second core; analyzing the packet at the first core to determine whether to transfer the packet to the second core of the integrated circuit; upon determining to transfer the packet to the second core, storing the packet in a switching circuit located in the first core polling the switching circuit in the first core to determine if the switching circuit has packets to be retrieved by the second core. - View Dependent Claims (28, 29, 30)
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Specification