Pulse signal output circuit and shift register

• US 8,718,224 B2
• Filed: 07/30/2012
• Issued: 05/06/2014
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Toyotaka, Kouhei
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US13/561,499
• Publication Number:
  US 20130034199A1
• Time in Patent Office: 645 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

To provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit includes a plurality of transistors each including an oxide semiconductor. In accordance with operations of the pulse signal output circuit, the threshold voltage of the transistor including an oxide semiconductor is changed. A shift register including the pulse signal output circuit is formed. A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Claims

1. A pulse signal output circuit comprising:

a first transistor to a tenth transistor each comprising a first terminal, a second terminal, a first gate terminal, and a second gate terminal;

a first to fourth input terminals;

a first output terminal and a second output terminal; and

a first to fourth power supply lines,

wherein;

the first terminal of the first transistor is electrically connected to the first input terminal, and the second terminal of the first transistor is electrically connected to the first output terminal,

the first terminal of the second transistor is electrically connected to the first output terminal, and the second terminal of the second transistor is electrically connected to the first power supply line,

the first terminal of the third transistor is electrically connected to the first input terminal, and the second terminal of the third transistor is electrically connected to the second output terminal,

the first terminal of the fourth transistor is electrically connected to the second output terminal, and the second terminal of the fourth transistor is electrically connected to the first power supply line,

the first terminal of the fifth transistor is electrically connected to the second power supply line, and the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the first terminal of the seventh transistor,

the second terminal of the sixth transistor is electrically connected to the first power supply line, and the first gate terminal of the sixth transistor is electrically connected to the second terminal of the eighth transistor, the first terminal of the ninth transistor, the first gate terminal of the second transistor, and the first gate terminal of the fourth transistor,

the second terminal of the seventh transistor is electrically connected to the first gate terminal of the first transistor and the first gate terminal of the third transistor, and the first gate terminal of the seventh transistor is electrically connected to the second power supply line,

the first terminal of the eighth transistor is electrically connected to the second terminal of the tenth transistor, the first gate terminal of the eighth transistor is electrically connected to the second input terminal, and the second gate terminal of the eighth transistor is electrically connected to the third power supply line,

the second terminal of the ninth transistor is electrically connected to the first power supply line,

the first terminal of the tenth transistor is electrically connected to the second power supply line, the first gate terminal of the tenth transistor is electrically connected to the third input terminal, and the second gate terminal of the tenth transistor is electrically connected to the third power supply line,

the first output terminal is electrically connected to the second gate terminal of the first transistor and the second gate terminal of the third transistor,

the fourth input terminal is electrically connected to the first gate terminal of the fifth transistor, the second gate terminal of the fifth transistor, and the first gate terminal of the ninth transistor,

the third power supply line is electrically connected to the second gate terminal of the second transistor, the second gate terminal of the fourth transistor, the second gate terminal of the sixth transistor, and the second gate terminal of the ninth transistor, and

the fourth power supply line is electrically connected to the second gate terminal of the seventh transistor.

2. The pulse signal output circuit according to claim 1, further comprising a capacitor,

wherein the capacitor is electrically connected to the first gate terminal of the second transistor, the first gate terminal of the fourth transistor, the first gate terminal of the sixth transistor, the second terminal of the eighth transistor, and the first terminal of the ninth transistor.

3. The pulse signal output circuit according to claim 1, further comprising an eleventh transistor, wherein:

a first terminal of the eleventh transistor is electrically connected to the second power supply line, and

a second terminal of the eleventh transistor is electrically connected to the first gate terminal of the second transistor, the first gate terminal of the fourth transistor, the first gate terminal of the sixth transistor, the second terminal of the eighth transistor, and the first terminal of the ninth transistor.

4. The pulse signal output circuit according to claim 1, wherein:

a second potential of the second power supply line is higher than a first potential of the first power supply line,

a third potential of the fourth power supply line is higher than the first potential and lower than the second potential, and

a fourth potential of the third power supply line is lower than the third potential.

5. The pulse signal output circuit according to claim 1, wherein:

a first clock signal is input to the first input terminal,

a second clock signal is input to the second input terminal,

a third clock signal is input to the third input terminal, and

a fourth clock signal is input to the fourth input terminal.

6. A shift register comprising the pulse signal output circuit according to claim 1.

7. The pulse signal output circuit according to claim 1, wherein a channel formation region of each of the first transistor to the tenth transistor comprises an oxide semiconductor.

8. The pulse signal output circuit according to claim 1, wherein a ratio W/L of a channel width W to a channel length L of the first transistor and a ratio W/L of a channel width W to a channel length L of the third transistor are each larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor.

9. The pulse signal output circuit according to claim 1,

wherein a ratio W/L of a channel width W to a channel length L of the fifth transistor is larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor, and

wherein the ratio W/L of the channel width W to the channel length L of the fifth transistor is larger than or equal to a ratio W/L of a channel width W to a channel length L of the seventh transistor.

10. The pulse signal output circuit according to claim 1, wherein a ratio W/L of a channel width W to a channel length L of the third transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor.

11. A pulse signal output circuit comprising:

a first to ninth transistors each comprising a first terminal, a second terminal, a first gate terminal, and a second gate terminal;

a first to third input terminals;

a first output terminal and a second output terminal; and

a first to fourth power supply lines,

wherein;

the first terminal of the first transistor is electrically connected to the first input terminal, and the second terminal of the first transistor is electrically connected to the first output terminal,

the first terminal of the second transistor is electrically connected to the first output terminal, and the second terminal of the second transistor is electrically connected to the first power supply line,

the first terminal of the third transistor is electrically connected to the first input terminal, and the second terminal of the third transistor is electrically connected to the second output terminal,

the first terminal of the fourth transistor is electrically connected to the second output terminal, and the second terminal of the fourth transistor is electrically connected to the first power supply line,

the first terminal of the fifth transistor is electrically connected to the second power supply line, and the second terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor and the first terminal of the seventh transistor,

the second terminal of the sixth transistor is electrically connected to the first power supply line, and the first gate terminal of the sixth transistor is electrically connected to the second terminal of the eighth transistor, the first terminal of the ninth transistor, the first gate terminal of the second transistor, and the first gate terminal of the fourth transistor,

the second terminal of the seventh transistor is electrically connected to the first gate terminal of the first transistor and the first gate terminal of the third transistor, and the first gate terminal of the seventh transistor is electrically connected to the second power supply line,

the first terminal of the eighth transistor is electrically connected to the first input terminal, the first gate terminal of the eighth transistor is electrically connected to the second input terminal, and the second gate terminal of the eighth transistor is electrically connected to the third power supply line,

the second terminal of the ninth transistor is electrically connected to the first power supply line,

the first output terminal is electrically connected to the second gate terminal of the first transistor and the second gate terminal of the third transistor,

the third input terminal is electrically connected to the first gate terminal of the fifth transistor, the second gate terminal of the fifth transistor, and the first gate terminal of the ninth transistor,

the third power supply line is electrically connected to the second gate terminal of the second transistor, the second gate terminal of the fourth transistor, the second gate terminal of the sixth transistor, and the second gate terminal of the ninth transistor, and

the fourth power supply line is electrically connected to the second gate terminal of the seventh transistor.

12. The pulse signal output circuit according to claim 11, further comprising a capacitor,

wherein the capacitor is electrically connected to the first gate terminal of the second transistor, the first gate terminal of the fourth transistor, the first gate terminal of the sixth transistor, the second terminal of the eighth transistor, and the first terminal of the ninth transistor.

13. The pulse signal output circuit according to claim 11, further comprising a tenth transistor, wherein:

a first terminal of the tenth transistor is electrically connected to the second power supply line, and

a second terminal of the tenth transistor is electrically connected to the first gate terminal of the second transistor, the first gate terminal of the fourth transistor, the first gate terminal of the sixth transistor, the second terminal of the eighth transistor, and the first terminal of the ninth transistor.

14. The pulse signal output circuit according to claim 11, wherein:

a second potential of the second power supply line is higher than a first potential of the first power supply line,

a third potential of the fourth power supply line is higher than the first potential and lower than the second potential, and

a fourth potential of the third potential power supply line is lower than the third potential.

15. The pulse signal output circuit according to claim 11, wherein:

a first clock signal is input to the first input terminal,

a second clock signal is input to the second input terminal, and

a third clock signal is input to the third input terminal.

16. A shift register comprising the pulse signal output circuit according to claim 11.

17. The pulse signal output circuit according to claim 11, wherein a channel formation region of each of the first transistor to the ninth transistor comprises an oxide semiconductor.

18. The pulse signal output circuit according to claim 11, wherein a ratio W/L of a channel width W to a channel length L of the first transistor and a ratio W/L of a channel width W to a channel length L of the third transistor are each larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor.

19. The pulse signal output circuit according to claim 11,

wherein a ratio W/L of a channel width W to a channel length L of the fifth transistor is larger than a ratio W/L of a channel width W to a channel length L of the sixth transistor, and

wherein the ratio W/L of the channel width W to the channel length L of the fifth transistor is larger than or equal to a ratio W/L of a channel width W to a channel length L of the seventh transistor.

20. The pulse signal output circuit according to claim 11, wherein a ratio W/L of a channel width W to a channel length L of the third transistor is larger than a ratio W/L of a channel width W to a channel length L of the fourth transistor.