Translated memory protection apparatus for an advanced microprocessor

• US 8,719,544 B2
• Filed: 09/23/2011
• Issued: 05/06/2014
• Est. Priority Date: 08/22/1996
• Status: Expired due to Fees

• Current Assignee: Liberty Patents LLC
• Original Assignee: Edmund J. Kelly, Malcolm J. Wing, Robert F. Cmelik
• Inventors: Kelly, Edmund J., Cmelik, Robert F., Wing, Malcolm J.
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US13/243,943
• Publication Number:
  US 20120110306A1
• Time in Patent Office: 956 Days
• Field of Search: 711/100, 711/147, 711/154, 711/200, 711202-203, 711206-207, 714/9, 714/53, 714/723
• US Class Current: 711/206
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Claims

1. A method comprising:

responsive to an attempt to execute a plurality of source instructions, translating the source instructions into a plurality of translated instructions;

modifying the translated instructions to form a plurality of modified translated instructions, wherein the modifying comprises changing an execution order of at least one instruction in the translated instructions; and

storing and executing the modified translated instructions.

2. The method of claim 1, wherein the modifying comprises:

eliminating at least one instruction from the translated instructions.

3. The method of claim 1, wherein the modifying comprises:

renaming a portion of at least one instruction of the translated instructions.

4. The method of claim 1, wherein the translated instructions include a loop, and wherein the modifying comprises:

moving at least one instruction out of the loop of the translated instructions.

5. The method of claim 1, further comprising:

responsive to a subsequent attempt to execute the source instructions, retrieving and executing the modified translated instructions.

6. The method of claim 1, wherein the modifying comprises:

determining whether to modify the plurality of translated instructions; and

responsive to a determination to modify the plurality of translated instructions, modifying the translated instructions to form the plurality of modified translated instructions.

7. A method comprising:

responsive to an attempt to execute a plurality of source instructions, determining whether the source instructions have been translated into a plurality of stored translated instructions;

if the source instructions have been translated into the translated instructions, executing the stored translated instructions; and

if the source instructions are untranslated, translating the source instructions into a plurality of translated instructions,

modifying the translated instructions to form a plurality of modified translated instructions, wherein the modifying comprises changing an execution order of at least one instruction in the translated instructions, and

storing and executing the modified translated instructions.

8. The method of claim 7, wherein the modifying comprises:

eliminating at least one instruction from the translated instructions.

9. The method of claim 7, wherein the modifying comprises:

renaming a portion of at least one instruction of the translated instructions.

10. The method of claim 7, wherein the translated instructions include a loop, and wherein the modifying comprises:

moving at least one instruction out of the loop of the translated instructions.

11. The method of claim 7, further comprising:

responsive to a subsequent attempt to execute the source instructions, retrieving and executing the modified translated instructions.

12. The method of claim 7, wherein the modifying comprises:

determining whether to modify the plurality of translated instructions; and

responsive to a determination to modify the plurality of translated instructions, modifying the translated instructions to form the plurality of modified translated instructions.

13. An apparatus comprising:

means for translating a plurality of source instructions into a plurality of translated instructions responsive to an attempt to execute the source instructions;

means for modifying the translated instructions to form a plurality of modified translated instructions, wherein the means for modifying comprises means for changing an execution order of at least one instruction in the translated instructions;

means for storing the modified translated instructions; and

means for executing the modified translated instructions.

14. The apparatus of claim 13, wherein the means for modifying comprises:

means for eliminating at least one instruction from the translated instructions.

15. The apparatus of claim 13, wherein the means for modifying comprises:

means for renaming a portion of at least one instruction of the translated instructions.

16. The apparatus of claim 13, wherein the translated instructions include a loop, and wherein the means for modifying comprises:

means for moving at least one instruction out of the loop of the translated instructions.

17. The apparatus of claim 13, wherein the means for storing comprises a translation memory buffer.