Configurable encoder for cyclic error correction codes

• US 8,719,678 B2
• Filed: 10/23/2013
• Issued: 05/06/2014
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Anholt, Micha
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US14/060,748
• Publication Number:
  US 20140053046A1
• Time in Patent Office: 195 Days
• Field of Search: 714/789
• US Class Current: 714/781
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/159 Remainder calculation, e.g. for encoding and syndrome calculation
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end

Abstract

Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

Claims

1. An Error Correction Code (ECC) encoder, comprising:

a first processing stage configured to;

receive input data; and

encode the received input data dependent upon a first set of coefficients to produce a first output;

a second processing stage configured to;

receive the first output from the first processing stage; and

encode the first output dependent upon a second set of coefficients to produce a second output;

and

a control circuit coupled to the first processing stage and the second processing stage, wherein the control circuit is configured to;

select an operating mode;

activate the first processing stage;

activate the second processing stage dependent upon the selected operating mode; and

select an output of the ECC encoder from the output of the first output or the second output dependent upon the selected operating mode.

2. The ECC encoder according to claim 1, wherein the control circuit is further configured to modify at least one coefficients of the first set of coefficients or of the second set of coefficients.

3. The ECC encoder according to claim 1, wherein at least one coefficients of the first set of coefficients or of the second set of coefficients is fixed.

4. The ECC encoder according to claim 1, wherein the control circuit is further configured to modify one of the first set of coefficients or the second set of coefficients, and wherein the other of the first set of coefficients or the second set of coefficients is fixed.

5. The ECC encoder according to claim 1, wherein the first output has a first maximum number of correctable errors, and wherein the second output has a second maximum number of correctable errors, wherein the second maximum number is larger than the first maximum number.

6. The ECC encoder according to claim 1, further comprising a clock source coupled to the first processing stage and the second processing stage, wherein the first processing stage is further configured to accept and process multiple bits of the input data in each cycle of the clock source, and wherein the second processing stage is further configured to accept and process at least two bits of the first output in each cycle of the clock source.

7. The ECC encoder according to claim 1, wherein the control circuit is further configured to deactivate the second processing stage responsive to receiving a request to enter a low power operating mode.

8. A method, comprising:

filtering input data using a first processing stage dependent upon a first set of coefficients representing a first Error Correction Code (ECC) to produce a first output;

filtering the first output using a second processing stage dependent upon a second set of the coefficients representing a second ECC to produce a second output;

generating a first redundancy output corresponding to the first ECC dependent upon on the first output while operating in a first mode, wherein while operating in the first mode, the second processing stage is inactive; and

generating a second redundancy output corresponding to the second ECC dependent upon on the second output while operating in a second mode.

9. The method of claim 8, wherein the first set of coefficients belong to a first generator polynomial representing the first ECC and the second set of coefficients belong to a quotient polynomial, wherein the quotient polynomial is a second generator polynomial representing the second ECC divided by the first generator polynomial.

10. The method of claim 9, wherein filtering input data to produce the first output comprises calculating a bit-wise exclusive-OR (XOR) between the input data and the first generator polynomial.

11. The method of claim 10, wherein filtering the first output to produce a second output comprises calculating a bit-wise XOR between the input data and the second output.

12. The method of claim 8, further comprising constructing a first code word using the input data and the first redundancy output while operating in the first mode, and constructing a second code word using the input data and the second redundancy output while operating in the second mode.

13. The method of claim 8, further comprising receiving a request to encode the input data with one of the first ECC or the second ECC, and selecting one of the first mode or the second mode responsive to the request.

14. The method of claim 8, further comprising receiving a request to reduce power consumption and selecting the first mode responsive to the request.

15. A memory controller system, comprising:

a memory device interface;

a host interface configured to receive data from a host;

a first Error Correction Code (ECC) stage, coupled to the host interface, wherein the first ECC stage is configured to encode the received data dependent upon a first set of coefficients to produce a first output;

a second ECC stage, coupled to the first ECC stage, wherein the second ECC stage is configured to;

receive the first output from the first ECC stage; and

encode the first output dependent upon a second set of coefficients to produce a second output;

and

a processor coupled to the first processing stage and to the second processing stage, wherein the processor is configured to;

select an operating mode;

activate the first ECC stage;

activate the second ECC stage dependent upon the selected operating mode; and

selectively, couple one of the first output or the second output to the memory device interface dependent upon the selected operating mode.

16. The system of claim 15, further comprising a third ECC stage, coupled to the second ECC stage, wherein the third ECC stage is configured to:

receive the first output from the first ECC stage; and

encode the second output dependent upon a third set of coefficients to produce a third output.

17. The system of claim 15, wherein the first set of coefficients belong to a first generator polynomial representing a first ECC code and the second set of coefficients belong to a quotient polynomial, wherein the quotient polynomial is a second generator polynomial representing a second ECC code divided by the first generator polynomial.

18. The system of claim 17, wherein the first ECC code has a first maximum number of correctable errors, and the second ECC code has a second maximum number of correctable errors, wherein the second maximum number of correctable errors is larger than the first maximum number of correctable errors.

19. The system of claim 15, wherein the first ECC stage comprises a first Bose-Chaudhuri-Hocquenghem (BCH) code, and wherein the second ECC stage comprises a second BCH code.

20. The system of claim 16, wherein the processor is further configured to:

activate the third ECC stage dependent upon the selected operating mode;

couple the third output to the memory device interface dependent upon the selected operating mode;

deactivate the third ECC stage responsive to selecting a first low power operating mode; and

deactivate the second ECC stage and the third ECC stage responsive to selecting a second low power operating mode.