Method and apparatus for identifying double patterning loop violations

• US 8,719,737 B1
• Filed: 07/20/2012
• Issued: 05/06/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Wang, Xiaojun
• Primary Examiner(s): Nguyen, Nha
• Assistant Examiner(s): Ngo, Brian
• Application Number:
  US13/555,058
• Time in Patent Office: 655 Days
• Field of Search: 716/50, 716/51, 716/52, 716/53, 716/54, 716/110, 716/111, 716/119, 716/139
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.

Claims

1. A non-transitory machine readable medium storing a program for detecting design rule violations in a multi-layer circuit design layout including a plurality of shapes, the program comprising sets of instructions for:

identifying a plurality of disjoint sets of shapes that each comprises a number of shapes on one layout layer that are each within a threshold distance from at least one other shape in a same disjoint set of shapes, wherein no shape within a disjoint set is within the threshold distance of any shape in another disjoint set;

in each particular disjoint set of a group of disjoint sets, identifying at least one subset of shapes that forms a loop of shapes that includes at least three shapes and includes only shapes of the particular disjoint set that are each within a threshold distance from at least two other shapes in the particular disjoint set, wherein at least one particular loop of one identified particular subset wholly contains at least one shape that is not part of the identified particular subset;

examining different identified subsets of shapes to identify any identified subset that violates a design rule; and

for each identified particular subset of shapes that violates a design rule, displaying a marker near the identified particular subset of shapes to visually aid a user to identify and resolve the design rule violation.

2. The non-transitory machine readable medium of claim 1, wherein the set of instructions for identifying the plurality of disjoint sets of shapes comprises a set of instructions for connecting with a link each pair of shapes in the plurality of shapes that are within the threshold distance.

3. The non-transitory machine readable medium of claim 1, wherein the threshold distance defines that two shapes within the threshold distance should be assigned to different mask layouts.

4. The non-transitory machine readable medium of claim 2, wherein the set of instructions for identifying the plurality of disjoint sets of shapes further comprises a set of instructions for identifying a set of shapes in which all shapes are connected to each other by one or more links and shapes.

5. The non-transitory machine readable medium of claim 4, wherein the set of instructions for examining different identified subsets of shapes to identify any identified subset that violates a design rule comprises sets of instructions for:

for each identified subset;

assigning shapes in the subset of shapes to two different mask layouts; and

determining whether the subset includes at least one pair of shapes connected by a link and assigned to a same mask layout.

6. The non-transitory machine readable medium of claim 5, wherein the set of instructions for determining whether each subset includes the at least one pair of shapes comprises a set of instructions for tracing a graph that is formed by the shapes in the disjoint set and links connecting the shapes.

7. The non-transitory machine readable medium of claim 6, wherein the set of instructions for tracing the graph comprises a set of instructions for using a breadth-first search.

8. The non-transitory machine readable medium of claim 2, wherein the set of instructions for examining different identified subsets of shapes to identify any identified subset that violates a design rule comprises a set of instructions for tracing a graph that is formed by the shapes in each subset and links connecting the shapes (1) to identify a pair of shapes in the subset of shapes that violate the design rule and (2) to identify one or more shapes in the subset of shapes that are not part of the loop.

9. The non-transitory machine readable medium of claim 8, wherein the set of instructions for tracing the graph comprises a set of instructions for using a breadth-first search.

10. The non-transitory machine readable medium of claim 4, wherein the set of instructions for identifying the plurality of disjoint sets further comprises sets of instructions for:

for each disjoint set of the plurality of disjoint sets;

assigning shapes in the disjoint set to two different mask layouts;

identifying all pairs of shapes in the disjoint set that are connected by a link and assigned to a same mask layout; and

identifying all subsets of shapes in the disjoint set that include at least one identified pair of shapes.

11. The non-transitory machine readable medium of claim 1, wherein the marker identifies all of the shapes in the subset of shapes that violates the design rule.

12. The non-transitory machine readable medium of claim 1, wherein the violated design rule is a double patterning rule violation.

13. The machine readable medium of claim 1, wherein at least a first identified subset that forms a first loop wholly contains a second identified subset that forms a second loop.

14. A system comprising:

a processor for executing sets of instructions; and

a memory for storing a computer program for correcting design rule violations in a multi-layer circuit design layout including a plurality of shapes, the program comprising sets of instructions for;

identifying a plurality of disjoint sets of shapes that each comprises a number of shapes on one layout layer that are each within a threshold distance from at least one other shape in the same disjoint set of shapes, wherein no shape within a disjoint set is within the threshold distance of any shape in another disjoint set;

in each particular disjoint set of a group of disjoint sets, identifying at least one subset of shapes that forms a loop of shapes that includes at least three shapes and includes only shapes of the particular disjoint set that are each within a threshold distance from at least two other shapes in the particular disjoint set, wherein at least one particular loop of one identified particular subset wholly contains at least one shape that is not part of the identified particular subset;

examining different identified subsets of shapes to identify any identified subset that violates a design rule; and

for each identified particular subset of shapes that violates a design rule, displaying a marker near the identified particular subset of shapes to visually aid a user to identify and resolve the design rule violation.

15. The system of claim 14, wherein the set of instructions for examining different identified subsets comprises a set of instructions for assigning shapes in the subset to two different mask layouts.

16. The system of claim 15, wherein the set of instructions for examining different identified subsets further comprises a set of instructions for determining whether the subset includes at least one pair of shapes that are (i) within the threshold distance and (ii) assigned to a same mask layout.

17. A computer-implemented method for detecting design rule violations in a multi-layer circuit design layout including a plurality of shapes, the method comprising:

identifying a plurality of disjoint sets of shapes that each comprises a number of shapes on one layout layer that are each within a threshold distance from at least one other shape in the same disjoint set of shapes, wherein no shape within a disjoint set is within the threshold distance of any shape in another disjoint set;

in each particular disjoint set of a group of disjoint sets, identifying at least one subset of shapes that forms a loop of shapes that includes at least three shapes and includes only shapes of the particular disjoint set that are each within a threshold distance from at least two other shapes in the particular disjoint set, wherein at least one particular loop of one identified particular subset wholly contains at least one shape that is not part of the identified particular subset;

examining different identified subsets of shapes to identify any identified subset that violates a design rule; and

for each identified particular subset of shapes that violates a design rule, displaying, at a computer, a marker near the identified particular subset of shapes to visually aid a user to identify and resolve the design rule violation.

18. The method of claim 17, wherein examining different identified subsets of shapes comprises assigning shapes in the different identified subsets to two different mask layouts.

19. The method of claim 18, wherein examining different identified subsets of shapes further comprises identifying all pairs of shapes in the disjoint set that are assigned to a same mask layout.