Placement and routing of a circuit design

• US 8,719,750 B1
• Filed: 11/12/2012
• Issued: 05/06/2014
• Est. Priority Date: 11/12/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Balzli, Robert M. Jr.
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/674,889
• Time in Patent Office: 540 Days
• Field of Search: 716/113, 716/116, 716/118, 716/119, 716/126
• US Class Current: 716/113
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Approaches for placing and routing a circuit design on a programmable integrated circuit (IC) are disclosed. One partial reconfiguration (PR) resource portion of the circuit design is selected from a plurality of PR resource portions of the design. Uncontained resources in the PR resource portion is identified. The PR resource portion, less the uncontained resources, is placed in an assigned region, and the uncontained resources is placed on the programmable IC unconstrained by the assigned region of the PR resource portion. The design is routed from the placed PR resource portion to the placed uncontained resources, and the process is repeated for each unplaced PR resource portion. After placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, unplaced portions of the circuit design are placed and routed.

Claims

1. A method of placing and routing a circuit design on a programmable integrated circuit (IC), comprising:

on one or more programmed processors, performing operations including;

selecting one partial reconfiguration (PR) resource portion of the circuit design from a plurality of PR resource portions of the circuit design, wherein each PR resource portion is assigned to a respective region of the programmable IC;

identifying uncontained resources in the selected PR resource portion;

placing the selected PR resource portion, less the uncontained resources, in the respective region;

placing the uncontained resources on the programmable IC unconstrained by the respective region;

routing from the selected PR resource portion placed in the respective region to the placed uncontained resources;

repeating the selecting, the identifying, the placing the selected PR resource portion, the placing the uncontained resources, and the routing for each unplaced PR resource portion; and

after placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, placing and routing unplaced portions of the circuit design.

2. The method of claim 1, wherein:

the routing from the selected PR resource portion placed in the respective region to the placed uncontained resources includes reserving at least one resource of the programmable IC on a route from the selected PR resource portion to the placed uncontained resources; and

the placing and routing of the unplaced portions avoids placing and routing with the at least one resource.

3. The method of claim 1, further comprising, after the placing the plurality of PR resource portions and routing to the uncontained resources in the plurality of PR resource portions, routing resources within each of the plurality of PR resource portions.

4. The method of claim 1, wherein the routing from the selected PR resource portion placed in the respective region to the placed uncontained resource includes,

excluding one or more resources of the programmable IC from eligibility for the routing, wherein the one or more resources include a resource on which no logic has been placed and no route has been assigned.

5. The method of claim 4, wherein at least one of the one or more resources includes a digital signal processor (DSP).

6. The method of claim 4, wherein at least one of the one or more resources includes a block RAM (BRAM).

7. The method of claim 1, further comprising, after the placing and routing of the unplaced portions of the circuit design:

determining whether or not timing constraints are satisfied;

in response to determining that the timing constraints are not satisfied, performing operations including;

preserving a current placement;

removing all routing;

routing all nets of the circuit design after the removing;

after the routing all the nets, for top-level resources and routes that are not timing critical, removing placement and routing, and removing routes from the selected PR resource portion to the uncontained resources;

in an order from a net of the uncontained resources having a least amount of slack to a net of the uncontained resources having a greatest amount of slack, routing each net; and

after the routing each net in the order of the least amount of slack to the greatest amount of slack, placing and routing remaining unplaced portions of the circuit design.

8. The method of claim 7, further comprising, after the placing and routing remaining unplaced portions of the circuit design:

determining whether or not the timing constraints are satisfied;

in response to determining that the timing constraints are not satisfied, performing operations including;

removing all placement and routing;

placing all resources of the circuit design;

routing only portions of the circuit design that are timing critical;

after the routing only portions of the circuit design that are timing critical, routing from each PR resource portion to uncontained resources of the PR resource portion; and

after the routing from each PR resource portion to uncontained resources of the PR resource portion, routing remaining unrouted portions of the circuit design.

9. The method of claim 1, wherein the programmable IC is a field programmable gate array (FPGA), the FPGA includes an array of tiles, a plurality of the tiles include programmable logic, and a subset of the tiles include programmable interconnection points and a scarce resource, wherein the routing from the selected PR resource portion placed in the respective region to the placed uncontained resources includes,

excluding from consideration for routing from the selected PR resource portion to the placed uncontained resources a tile having a programmable interconnection point and a scarce resource.

10. The method of claim 1, wherein the uncontained resources are placed on an input/output block (IOB) of the programmable IC.

11. The method of claim 1, wherein the uncontained resources are placed on a gigabit transceiver (GT) of the programmable IC.

12. The method of claim 1, wherein the uncontained resources are placed on configuration logic of the programmable IC.

13. The method of claim 1, wherein the uncontained resources are placed on clock manager circuitry of the programmable IC.

14. A system for placing and routing a circuit design on a programmable integrated circuit (IC), comprising:

a processor; and

a memory arrangement coupled to the processor, wherein the memory arrangement is configured with instructions that are executable by the processor for causing the processor to perform the following operations;

selecting one partial reconfiguration (PR) resource portion of the circuit design from a plurality of PR resource portions of the circuit design, wherein each PR resource portion is assigned to a respective region of the programmable IC;

identifying uncontained resources in the selected PR resource portion;

placing the selected PR resource portion, less the uncontained resources, in the respective region;

placing the uncontained resources on the programmable IC unconstrained by the respective region;

routing from the selected PR resource portion placed in the respective region to the placed uncontained resources;

repeating the selecting, the identifying, the placing the selected PR resource portion, the placing the uncontained resources, and the routing for each unplaced PR resource portion; and

after placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, placing and routing unplaced portions of the circuit design.

15. The system of claim 14, the operations further including:

wherein the routing from the selected PR resource portion placed in the respective region to the placed uncontained resources includes reserving at least one resource of the programmable IC on a route from the selected PR resource portion to the placed uncontained resources; and

the placing and routing of the unplaced portions avoids placing and routing with the at least one resource.

16. The system of claim 14, the operations further including, after the placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, routing resources within each of the plurality of PR resource portions.

17. The system of claim 14, wherein the routing from the selected PR resource portion placed in the respective region to the placed uncontained resources includes,

excluding one or more resources of the programmable IC from eligibility for the routing, wherein the one or more resources include a resource on which no logic has been placed and no route has been assigned.

18. The system of claim 17, wherein at least one of the one or more resources includes a digital signal processor (DSP).

19. The system of claim 17, wherein at least one of the one or more resources includes a block RAM (BRAM).

20. The system of claim 14, wherein the programmable IC is a field programmable gate array (FPGA), the FPGA includes an array of tiles, a plurality of the tiles include programmable logic, and a subset of the tiles include programmable interconnection points and a scarce resource, wherein the routing from the selected PR resource portion placed in the respective region to the placed uncontained resources includes,

excluding from consideration for routing from the selected PR resource portion to the placed uncontained resources a tile having a programmable interconnection point and a scarce resource.