Method and apparatus for turning custom prototype boards into co-simulation, co-emulation systems

• US 8,719,762 B2
• Filed: 12/28/2012
• Issued: 05/06/2014
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Taiwan Co., Ltd. (Synopsys Incorporated)
• Inventors: Chang, Yingtsai, Shei, Sweyyan, Lin, Meng-Chyi, Mao, Hwa, Wang, Ming Yang, Hsu, Yuchin
• Primary Examiner(s): Do, Thuan
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/730,543
• Publication Number:
  US 20130117007A1
• Time in Patent Office: 494 Days
• Field of Search: 703/28, 716/106, 716/108, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 8/20 Software design

Abstract

A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.

Claims

1. An apparatus adapted to emulate a circuit design, the apparatus comprising:

a first board comprising;

at least one FPGA; and

at least one connector, the first board being defined by at least one or more description files; and

a second board adapted to be connected to the first board via the at least one connector, the second board comprising a controller adapted to control the emulation, the at least one FPGA configured to receive a partition of the circuit design in accordance with the description files when the apparatus is invoked to emulate the circuit design, each partition being associated with a verification module adapted to communicate with the controller, each verification module adapted to be generated in accordance with the partition and the description files, said controller being further adapted to;

run a plurality of emulation cycles;

transmit a plurality of input signals to the verification modules; and

receive a plurality of output signals from the verification modules, the output signals being generated by the partition in response to at least a subset of the plurality of input signals.

2. The apparatus of claim 1 wherein the plurality of input signals is generated by a software component running on a workstation in a co-simulation mode when the workstation is invoked to run the software component, wherein the controller is further adapted to transmit the plurality of output signals to the software component, and wherein the emulation cycles are controlled by clocks generated by the software component.

3. The apparatus of claim 1 further comprising:

a memory disposed on the second board and storing the plurality of input signal values, wherein said controller is further adapted to generate plurality of clock signals controlling the plurality of emulation cycles.

4. The apparatus of claim 3 wherein the controller is adapted to:

combine the plurality of output signal values to form and save the plurality of output signal values in the memory.

5. The apparatus of claim 2 further comprising:

a transactor integrated with at least one verification module and the least one verification module'"'"'s associated partition, wherein the transactor and the software component exchange messages, wherein at least a first portion of the partition is clocked by at least a first clock generated by the at least one FPGA, wherein the at least first clock is suspended during message transfer between the transactor and the software component, and wherein the at least first clock is reactivated after the message transfer is completed.

6. The apparatus of claim 5 further comprising:

a target component coupled to the partitioned circuit design, wherein the target component, the transactor and at least a second portion of the partition are clocked by at least a second clock generated either by the at least one FPGA or the target component, wherein the at least second clock is not suspended during message transfer between the transactor and the software component.