Methods of forming 3-D circuits with integrated passive devices

• US 8,722,459 B2
• Filed: 12/31/2012
• Issued: 05/13/2014
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sanders, Paul W., Jones, Robert E., Petras, Michael F.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Fernandes, Errol
• Application Number:
  US13/731,242
• Publication Number:
  US 20130143367A1
• Time in Patent Office: 498 Days
• Field of Search: 438/107, 438/109, 438/667, 257/728, 257684-700, 257/724, 257773-778
• US Class Current: 438/107
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Claims

1. A method for forming a 3-D integrated circuit, comprising:

forming an active device (AD) substrate having an AD region thereon with device contacts therein;

forming an isolator substrate separately from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;

forming an integrated passive device (IPD) substrate separately from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate, and wherein at least some of the TSVs in the isolator substrate are vertically aligned with at least some of the TSVs in the IPD substrate; and

forming a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in a same substrate, thereby providing a connection selected from a group consisting of a cross-under connection between two or more IPDs in the IPD zone, and a cross-over connection between two or more device contacts of the AD substrate, and wherein at least one of the IPDs has a first element located in the IPD zone and a second element located in the further interconnect zone.

2. The method of claim 1, wherein at least some of the TSVs in the isolator substrate are coupled to some of the device contacts in the AD region on the AD substrate.

3. The method of claim 1, wherein some of the IPDs are coupled to other of the IPDs via the further interconnect zone.

4. The method of claim 1, wherein the isolator substrate has a resistivity of 1000 ohm-cm or greater.

5. The method of claim 1, wherein the isolator substrate has a thickness in a range of 10 and 200 micrometers or larger.

6. The method of claim 1, wherein the IPD substrate has a resistivity of 1000 ohm-cm or greater.

7. The method of claim 1, wherein the AD substrate has a first thickness, the isolator substrate has a second thickness, and the IPD substrate has a third thickness, and at least one or both of the second and third thickness are at least 2-20 times the first thickness.

8. The method of claim 1, wherein the further interconnect zone includes an additional portion selected from a ground plane, and electrical shield, and an electromagnetic band gap structure.

9. The method of claim 1, further comprising a circuit element, wherein a first portion of the circuit element is formed in the IPD zone, and a second portion of the circuit element is formed in the further interconnect zone, and wherein the circuit element is selected from an RF transmission line with first and second conductive strips, and an inductor with an inductor loop and a patterned ground plane.

10. A method of forming a 3-D integrated circuit, comprising:

forming an active device (AD) substrate having an AD region thereon with device contacts therein;

forming an isolator substrate separately from the AD substrate and having one or more through-substrate-vias (TSVs) therein adapted to be coupled to one or more of the device contacts in the AD region of the AD substrate;

forming an integrated passive device (IPD) substrate separately from the AD substrate and the isolator substrate and having an IPD zone on its surface in which IPDs have been formed, and having a plurality of TSVs formed underlying the IPD zone through the IPD substrate, wherein the TSVs in the IPD substrate are coupled with the IPDs in the IPD zone, and at least some of the TSVs are adapted to couple one or more of the IPDs in the IPD zone to TSVs in the isolator substrate;

forming a further interconnect zone located between the isolator substrate and the IPD substrate, wherein the further interconnect zone includes a lateral conductor between two or more TSVs in the IPD substrate, thereby providing a cross-under connection between two or more IPDs in the IPD zone; and

forming a circuit element, wherein a first portion of the circuit element is formed in the IPD zone, and a second portion of the circuit element is formed in the further interconnect zone.

11. The method of claim 10, wherein the further interconnect zone includes a ground plane.

12. The method of claim 10, wherein the further interconnect zone includes an electrical shield.

13. The method of claim 10, wherein the further interconnect zone includes an electromagnetic band gap structure having one or more tuned elements.

14. The method of claim 10, wherein the circuit element is an RF transmission line, the first portion of the circuit element is a first conductive strip of the RF transmission line, and the second portion of the circuit element is a second conductive strip of the RF transmission line.

15. The method of claim 14, wherein the first conductive strip and the second conductive strip form a differential signal pair.

16. The method of claim 14, wherein the second conductive strip is a ground.

17. The method of claim 10, wherein the circuit element is an inductor, the first portion of the circuit element is an inductor loop, and the second portion is a patterned ground plane.