Method and system for template assisted wafer bonding

• US 8,722,464 B2
• Filed: 04/24/2013
• Issued: 05/13/2014
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Skorpios Technologies Inc.
• Original Assignee: Skorpios Technologies Inc.
• Inventors: Dallesasse, John, Krasulick, Stephen B.
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/869,408
• Publication Number:
  US 20130302920A1
• Time in Patent Office: 384 Days
• Field of Search: 257/E21.513
• US Class Current: 438/113
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1204 Optical Diode
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 31/1876 Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06

Abstract

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Claims

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a first substrate having a device surface and one or more semiconductor devices thereon;

providing a compound semiconductor substrate including epitaxial compound semiconductor materials;

dicing the compound semiconductor substrate to provide a plurality of compound semiconductor dies;

providing a second substrate;

mounting the plurality of compound semiconductor dies on predetermined portions of the second substrate;

aligning the first substrate and the second substrate; and

bonding the first substrate to the second substrate to form a composite semiconductor structure, wherein the plurality of compound semiconductor dies are joined to the device surface of the first substrate.

2. The method of claim 1 wherein the first substrate comprises a silicon substrate or an SOI substrate.

3. The method of claim 2 wherein the second substrate comprises a silicon substrate or an SOI substrate.

4. The method of claim 1 wherein the compound semiconductor substrate comprises a III-V wafer or a II-VI wafer.

5. The method of claim 4 wherein the epitaxial compound semiconductor materials comprises III-V materials or II-VI materials.

6. The method of claim 1 wherein the one or more semiconductor devices comprise at least one of a CMOS device, a BiCMOS device, an NMOS device, a PMOS device, a detector, or a CCD.

7. The method of claim 1 further comprising, after bonding the first substrate to the second substrate, removing a portion of the second substrate to expose the plurality of compound semiconductor dies.

8. The method of claim 7 further comprising, after removing a portion of the second substrate, defining one or more photonic devices on one or more of the plurality of compound semiconductor dies.

9. The method of claim 8 further comprising forming electrical interconnects to the one or more photonic devices.

10. The method of claim 8 wherein the one or more photonic devices comprise at least one of a laser, a detector, or a modulator.

11. The method of claim 8 further comprising, after defining the one or more photonic devices, forming one or more waveguides in another portion of the second substrate, wherein each of the one or more waveguides is operable to optically connect a respective subset of the one or more photonic devices.

12. The method of claim 1 wherein each compound semiconductor die comprises one or more photonic devices.

13. The method of claim 12 wherein the one or more photonic devices comprise at least one of a laser, a detector, or a modulator.

14. A method of fabricating a composite semiconductor structure, the method comprising:

providing a first substrate having a bonding surface;

providing a compound semiconductor seed wafer;

dicing the compound semiconductor seed wafer to provide one or more compound semiconductor seed dies;

providing a second substrate;

mounting the one or more compound semiconductor seed dies on predetermined portions of the second substrate;

bonding the second substrate to the first substrate, wherein the one or more compound semiconductor seed dies are joined to the bonding surface of the first substrate;

removing a portion of the second substrate;

exposing at least a portion of a surface of the one or more compound semiconductor seed dies; and

growing epitaxial compound semiconductor layers on the exposed surface of the one or more compound semiconductor seed dies.

15. The method of claim 14 wherein the first substrate comprises a silicon substrate or an SOI substrate.

16. The method of claim 15 wherein the second substrate comprises a silicon substrate or an SOI substrate.

17. The method of claim 14 wherein the compound semiconductor seed wafer comprises a III-V wafer or a II-VI wafer.

18. The method of claim 17 wherein the epitaxial compound semiconductor layers comprise III-V materials or II-VI materials.

19. The method of claim 14 wherein the first substrate comprises doped regions associated with semiconductor devices.

20. The method of claim 19 further comprising, after growing epitaxial compound semiconductor layers, fabricating gate metals on the doped regions of the first substrate.