High-K dielectric stack and method of fabricating same

• US 8,722,484 B2
• Filed: 01/14/2008
• Issued: 05/13/2014
• Est. Priority Date: 01/14/2008
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Lisiansky, Michael, Roizin, Yakov, Heiman, Alexey, Fenigstein, Amos
• Primary Examiner(s): Coleman, William D
• Application Number:
  US12/014,073
• Publication Number:
  US 20090181530A1
• Time in Patent Office: 2,311 Days
• Field of Search: None
• US Class Current: 438/216
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to the crystallization temperature of the high-k dielectric material, thereby transforming the high-k dielectric material from an amorphous state to a crystalline state, and causing nitrogen atoms to diffuse into the insulating layer.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming an insulating layer over a semiconductor substrate;

forming an amorphous high-k dielectric layer over the insulating layer;

doping the amorphous high-k dielectric layer with nitrogen;

heating the amorphous high-K dielectric layer to a temperature that equals or exceeds the crystallization temperature of the amorphous high-K dielectric layer, thereby transforming the amorphous high-K dielectric layer to a crystalline high-k dielectric layer, and causing nitrogen to diffuse from the amorphous high-k dielectric layer into the insulating layer;

forming a conductive electrode layer over the crystalline high-k dielectric layer.

2. The method of claim 1, wherein the insulating layer comprises silicon oxide.

3. The method of claim 1, wherein the conductive electrode layer comprises metal or nitrided metal.

4. The method of claim 1, wherein the conductive electrode layer comprises polysilicon.

5. The method of claim 1, wherein the amorphous high-k dielectric layer comprises a metal oxide.

6. The method of claim 1, further comprising forming a silicon nitride/oxynitride layer over the insulating layer and forming the amorphous high-k dielectric layer over the silicon nitride/oxynitride layer.

7. The method of claim 1, further comprising removing a portion of the crystalline high-k dielectric layer over a first region of the substrate prior to forming the conductive electrode layer.

8. The method of claim 1, further comprising:

forming a gate dielectric layer over the semiconductor substrate;

forming a floating gate layer over the gate dielectric layer; and

forming the insulating layer over the floating gate layer.

9. The method of claim 1, further comprising:

forming an electrode structure comprising a metal over the semiconductor substrate; and

forming the insulating layer over the electrode structure.

10. The method of claim 1, further comprising:

forming a dielectric region over the semiconductor substrate;

forming an electrode structure comprising a metal over the dielectric region; and

forming the insulating layer over the electrode structure.

11. The method of claim 1, further comprising:

forming a second high-k dielectric layer on the first high-k dielectric layer, wherein the first high-k dielectric layer has a first crystallization temperature and the second high-k dielectric layer has a second crystallization temperature; and

annealing the first and second high-k dielectric layers at an anneal temperature that exceeds the first crystallization temperature.

12. The method of claim 1, wherein the amorphous high-k dielectric layer is doped with nitrogen by implanting nitrogen ions into the amorphous high-k dielectric layer.

13. The method of claim 1, wherein the amorphous high-k dielectric layer is doped with nitrogen by plasma treatment in a gas environment containing nitrogen atoms.

14. The method of claim 1, wherein the amorphous high-k dielectric layer is doped with nitrogen by a bake in a gas environment containing nitrogen atoms.

15. The method of claim 5, wherein the amorphous high-k dielectric layer comprises alloys of metal oxides.

16. The method of claim 5, wherein the amorphous high-k dielectric layer comprises alumina.

17. The method of claim 15, wherein the amorphous high-k dielectric layer comprises alloys of metal oxides with silicates and nitrides.

18. The method of claim 6, further comprising forming the silicon nitride/oxynitride layer to a thickness of about 10 to 20 Angstroms.

19. The method of claim 11, wherein the anneal temperature is less than the second crystallization temperature.

20. The method of claim 11, further comprising:

forming a third high-k dielectric layer on the second high-k dielectric layer; and

doping the third high-k dielectric layer with nitrogen.

21. The method of claim 20, wherein the first, second and third high-k dielectric layers comprise two or more different materials having two or more crystallization temperatures, the method further comprising annealing the first, second and third high-k dielectric layers at a temperature that equals or exceeds the highest crystallization temperature.

22. The method of claim 20, wherein the first, second and third high-k dielectric layers comprise two or more different materials having two or more crystallization temperatures, the method further comprising annealing the first, second and third high-k dielectric layers at a temperature that equals or exceeds the crystallization temperature of the first and third high-k dielectric layers.

23. The method of claim 12, further comprising implanting nitrogen with energies of about 10 eV to 15 keV, and a dosage in the range of E13-E16 cm⁻

2.

24. The method of claim 13, wherein the gas environment comprises N₂, N₂O, NO or NH3.