Process for through silicon via filling
First Claim
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1. A method of plating a through silicon via for connecting at least two integrated circuits, the method comprising:
- providing a structure containing a through silicon via hole, the structure comprising a seed layer within the through silicon via hole;
pretreating the seed layer using one or more liquids selected from the group consisting of water, a dilute acidic solution, a dilute basic solution, a surfactant containing solution, and the plating solution;
contacting the pretreated seed layer with a plating solution having copper ions at a concentration of at least about 40 grams per liter; and
while contacting the pretreated seed layer with the plating solution, plating copper into the through silicon via hole to completely fill the through silicon via hole,wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.
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Abstract
A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
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Citations
31 Claims
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1. A method of plating a through silicon via for connecting at least two integrated circuits, the method comprising:
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providing a structure containing a through silicon via hole, the structure comprising a seed layer within the through silicon via hole; pretreating the seed layer using one or more liquids selected from the group consisting of water, a dilute acidic solution, a dilute basic solution, a surfactant containing solution, and the plating solution; contacting the pretreated seed layer with a plating solution having copper ions at a concentration of at least about 40 grams per liter; and while contacting the pretreated seed layer with the plating solution, plating copper into the through silicon via hole to completely fill the through silicon via hole, wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A copper plating solution for depositing copper in a through silicon via for connecting at least two integrated circuits, the copper plating solution comprising:
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copper ions at a concentration of at least about 40 grams per liter; sulfuric acid; an oxidizing agent, the oxidizing agent comprises one or more of the following;
a hydrogen peroxide solution, elemental oxygen, cerium ions, and iron ions;an accelerator comprising one or more of the following functional groups;
a polar sulfur group, an oxygen group, and a nitrogen group;a suppressor at a concentration higher than a concentration of the accelerator; and a leveler at a concentration higher than the concentration of the accelerator. - View Dependent Claims (27, 28, 29, 30, 31)
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Specification