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Process for through silicon via filling

  • US 8,722,539 B2
  • Filed: 10/11/2011
  • Issued: 05/13/2014
  • Est. Priority Date: 08/18/2008
  • Status: Active Grant
First Claim
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1. A method of plating a through silicon via for connecting at least two integrated circuits, the method comprising:

  • providing a structure containing a through silicon via hole, the structure comprising a seed layer within the through silicon via hole;

    pretreating the seed layer using one or more liquids selected from the group consisting of water, a dilute acidic solution, a dilute basic solution, a surfactant containing solution, and the plating solution;

    contacting the pretreated seed layer with a plating solution having copper ions at a concentration of at least about 40 grams per liter; and

    while contacting the pretreated seed layer with the plating solution, plating copper into the through silicon via hole to completely fill the through silicon via hole,wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.

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