Semiconductor device, power circuit, and manufacturing method of semiconductor device

• US 8,723,173 B2
• Filed: 09/22/2010
• Issued: 05/13/2014
• Est. Priority Date: 09/24/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takahashi, Kei, Ito, Yoshiaki
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/888,064
• Publication Number:
  US 20110068852A1
• Time in Patent Office: 1,329 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over a substrate;

a first conductive layer over the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer;

an insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer;

a third conductive layer over the insulating layer, wherein the third conductive layer comprises at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer;

a fourth conductive layer over the insulating layer, the fourth conductive layer being in contact with the first conductive layer through a first opening in the insulating layer; and

a fifth conductive layer over the insulating layer, the fifth conductive layer being in contact with the second conductive layer through a second opening in the insulating layer.

2. The semiconductor device according to claim 1, wherein the third conductive layer is located between the first conductive layer and the second conductive layer.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 1, wherein the third conductive layer comprises a second portion which is overlapped with the second conductive layer.

5. The semiconductor device according to claim 1,

wherein the first conductive layer serves as one of a source electrode and a drain electrode,

wherein the second conductive layer serves as the other of the source electrode and the drain electrode, and

wherein the third conductive layer serves as a gate electrode.

6. The semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are located on the same surface.

7. The semiconductor device according to claim 1, wherein the first conductive layer is located inside the third conductive layer.

8. A power circuit comprising the semiconductor device according to claim 1, wherein the power circuit changes output voltage by switching an on state and off state of the semiconductor device in accordance with a pulse signal input to the third conductive layer.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal region, and

wherein the crystal region is in contact with the first conductive layer and the second conductive layer.

10. The semiconductor device according to claim 1, wherein the third conductive layer is located inside the second conductive layer.

11. The semiconductor device according to claim 1, wherein the first conductive layer is located inside the third conductive layer, and

wherein the third conductive layer is located inside the second conductive layer.

12. The semiconductor device according to claim 1, wherein the second conductive layer is not overlapped with the first conductive layer.

13. The semiconductor device according to claim 1, wherein a bottom surface of the first conductive layer and the second conductive layer has a flat surface.

14. The semiconductor device according to claim 1, wherein a top surface of the first conductive layer and the second conductive layer has a flat surface.

15. The semiconductor device according to claim 1, wherein the fourth conductive layer and the fifth conductive layer are not in contact with the oxide semiconductor layer.

16. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a crystal region.

17. The semiconductor device according to claim 16, wherein the crystal region comprises In₂Ga₂ZnO₇ crystal.

18. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming a first conductive layer over the oxide semiconductor layer;

forming a second conductive layer over the oxide semiconductor layer;

forming an insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer;

forming a third conductive layer over the insulating layer, wherein the third conductive layer is formed so as to comprise at least a first portion which is overlapped with neither the first conductive layer nor the second conductive layer;

forming a fourth conductive layer over the insulating layer, wherein the fourth conductive layer is formed so as to be in contact with the first conductive layer through a first opening in the insulating layer; and

forming a fifth conductive layer over the insulating layer, wherein the fifth conductive layer is formed so as to be in contact with the second conductive layer through a second opening in the insulating layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the third conductive layer is formed so as to be located between the first conductive layer and the second conductive layer.

20. The method for manufacturing a semiconductor device according to claim 18, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

21. The method for manufacturing a semiconductor device according to claim 18, wherein the third conductive layer is formed so as to comprise a second portion which is overlapped with the second conductive layer.

22. The method for manufacturing a semiconductor device according to claim 18, wherein the first conductive layer and the second conductive layer is formed on the same surface.

23. The method for manufacturing a semiconductor device according to claim 18, wherein the third conductive layer is formed so as to locate inside surround the second conductive layer.

24. The method for manufacturing a semiconductor device according to claim 18, wherein the first conductive layer is formed so as to locate inside the third conductive layer.

25. The method for manufacturing a semiconductor device according to claim 18, wherein the second conductive layer is formed not to be overlapped with the first conductive layer.

26. The method for manufacturing a semiconductor device according to claim 18, wherein a bottom surface of the first conductive layer and the second conductive layer are formed to have a flat surface.

27. The method for manufacturing a semiconductor device according to claim 18, wherein a top surface of the first conductive layer and the second conductive layer are formed to have a flat surface.

28. The method for manufacturing a semiconductor device according to claim 18,

further comprising the step of forming a crystal region at an upper superficial portion of the oxide semiconductor layer by heating the oxide semiconductor layer,

wherein the first conductive layer and the second conductive layer are formed over and in contact with the crystal region.

29. The method for manufacturing a semiconductor device according to claim 28, wherein the crystal region is formed by heating the oxide semiconductor layer at 500°

C. or higher.