Thin film transistor, contact structure, substrate, display device, and methods for manufacturing the same

• US 8,723,174 B2
• Filed: 04/27/2011
• Issued: 05/13/2014
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakazawa, Makoto
• Primary Examiner(s): Tran, Tran
• Application Number:
  US13/701,379
• Publication Number:
  US 20130069061A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/43, 257/52, 257/57, 257/72, 257/83, 257/E29.273
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A TFT 17 provided on a substrate 3 is provided. The TFT 17 includes a gate electrode 31, a gate insulating film 32, a semiconductor 33, a source electrode 34, a drain electrode 35, and a protection film 36. The semiconductor 33 includes a metal oxide semiconductor. The semiconductor 33 has a source portion 33a which is in contact with the source electrode 34, a drain portion 33b which is in contact with the drain electrode 35, and a channel portion 33c which is exposed through the source electrode 34 and the drain electrode 35. A conductive layer 37 having a relatively small electrical resistance is formed in each of the source portion 33a and the drain portion 33b. The conductive layer 37 is removed from the channel portion 33c.

Claims

1. A contact structure provided on a substrate, comprising:

a gate line;

a gate insulating film covering the gate line;

a first terminal provided on the gate insulating film in the vicinity of the gate line;

a first electrode connected to the first terminal;

a protection film covering the first terminal and the first electrode; and

a second electrode provided on the protection film and connected to the first electrode via the first terminal,

wherein

the first terminal includes a metal oxide semiconductor,

the first terminal has a first connection portion having an upper surface in contact with the first electrode, a covered portion in contact with the protection film at an upper surface spaced apart from the first electrode, and a first exposed portion having an upper surface exposed between the first connection portion and the covered portion through the first electrode and the protection film,

a conductive layer having a relatively small electrical resistance is formed in an upper surface portion of each of the first connection portion and the first exposed portion, and

the second electrode is in contact with the upper surface of the first exposed portion.

2. A contact structure provided on a substrate, comprising:

an auxiliary gate electrode;

a gate insulating film covering the auxiliary gate electrode;

a second terminal provided on the gate insulating film;

a third electrode connected to the second terminal;

a protection film covering the second terminal and the third electrode; and

a connection electrode provided on the protection film and connected to the third electrode via the second terminal,

wherein

the second terminal includes a metal oxide semiconductor including a conductive layer having a relatively small electrical resistance in an upper surface portion thereof,

the second terminal has a third connection portion having an upper surface in contact with the third electrode and covered by the protection film, and a second exposed portion having an upper surface exposed through or covered by the third electrode and exposed through the protection film,

an electrode exposed portion at which an upper surface of the auxiliary gate electrode is exposed through the gate insulating film is formed in the vicinity of the second exposed portion, and

the connection electrode is in contact with the upper surfaces of the electrode exposed portion and the second exposed portion.

3. An active matrix drive type substrate comprising:

a plurality of source lines extending in parallel to each other;

a plurality of gate lines extending in parallel to each other perpendicularly to the source lines;

a plurality of pixel electrodes provided in respective grid-square-like sub-regions separated by the source lines and the gate lines; and

a plurality of thin film transistors corresponding to the respective pixel electrodes,

wherein

the thin film transistor includes;

a gate electrode;

a gate insulating film covering the gate electrode;

a semiconductor facing the gate electrode with the gate insulating film being interposed between the semiconductor and the gate electrode;

a source electrode and a drain electrode connected together via the semiconductor; and

a protection film covering the semiconductor, the source electrode, and the drain electrode,

the semiconductor includes a metal oxide semiconductor,

the semiconductor has a source portion having an upper surface in contact with the source electrode, a drain portion in contact with the drain electrode at an upper surface spaced apart from the source electrode, and a channel portion provided between the source and drain portions and having an upper surface exposed through the source and drain electrodes,

a conductive layer having a relatively small electrical resistance is formed in an upper surface portion of each of the source and drain portions, and

the conductive layer is removed from an upper surface portion of the channel portion,

the gate electrode is connected to one of the plurality of gate lines, the source electrode is connected to one of the plurality of source lines, and the drain electrode is connected to one of the plurality of pixel electrodes,

a first contact structure is provided in a connection portion between the drain electrode and the pixel electrode, the first contact structure includes;

one of the plurality of gate lines covered by the gate insulating film;

a first terminal provided on the gate insulating film in the vicinity of the one of the plurality of gate lines;

a first electrode connected to the first terminal;

a protection film covering the first terminal and the first electrode; and

a second electrode provided on the protection film and connected to the first electrode via the first terminal, wherein

the first terminal includes a metal oxide semiconductor,

the first terminal has a first connection portion having an upper surface in contact with the first electrode, a covered portion in contact with the protection film at an upper surface spaced apart from the first electrode, and a first exposed portion having an upper surface exposed between the first connection portion and the covered portion through the first electrode and the protection film,

a conductive layer having a relatively small electrical resistance is formed in an upper surface portion of each of the first connection portion and the first exposed portion,

the second electrode is in contact with the upper surface of the first exposed portion, and

the first electrode serves as the drain electrode, and the second electrode serves as the pixel electrode.

4. The substrate of claim 3, further comprising:

a plurality of auxiliary capacitor lines extending in parallel to the gate lines;

a common line extending in parallel to the source lines and connected to all of the auxiliary capacitor lines; and

a plurality of capacitors connected to the respective corresponding drain electrodes and the respective corresponding auxiliary capacitor lines,

a second contact structure is provided at a connection portion between the auxiliary capacitor line and the common line, the second contact structure includes;

an auxiliary gate electrode covered by the gate insulating film;

a second terminal provided on the gate insulating film;

a third electrode connected to the second terminal;

a protection film covering the second terminal and the third electrode; and

a connection electrode provided on the protection film and connected to the third electrode via the second terminal, wherein

the second terminal includes a metal oxide semiconductor including a conductive layer having a relatively small electrical resistance in an upper surface portion thereof,

the second terminal has a third connection portion having an upper surface in contact with the third electrode and covered by the protection film, and a second exposed portion having an upper surface exposed through or covered by the third electrode and exposed through the protection film,

an electrode exposed portion at which an upper surface of the auxiliary gate electrode is exposed through the gate insulating film is formed in the vicinity of the second exposed portion,

the connection electrode is in contact with the upper surfaces of the electrode exposed portion and the second exposed portion, and

the auxiliary gate electrode serves as one of the plurality of auxiliary capacitor lines, and the third electrode serves as the common line.

5. The substrate of claim 4, wherein

the metal oxide semiconductors of the semiconductor, the first terminal, and the second terminal are formed of the same material.

6. The substrate of claim 5, wherein

the metal oxide semiconductor of at least one of the first and second terminals has portions having different thicknesses.

7. The substrate of claim 5, wherein

the metal oxide semiconductor contains at least one of In, Ga, and Zn.

8. The substrate of claim 5, wherein

the pixel electrode and the connection electrode are formed of the same material.

9. A display device comprising an active matrix drive type substrate of claim 3.

10. The display device of claim 9, further comprising:

a plurality of pixels arranged in a matrix form.