Integrated field effect transistors with high voltage drain sensing

• US 8,723,178 B2
• Filed: 01/20/2012
• Issued: 05/13/2014
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: Monolithic Power Systems Incorporated
• Original Assignee: Monolithic Power Systems Incorporated
• Inventors: Li, Tiesheng
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US13/355,324
• Publication Number:
  US 20130187160A1
• Time in Patent Office: 844 Days
• Field of Search: 257/57
• US Class Current: 257/57
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.

Claims

1. An integrated circuit comprising:

a power metal oxide semiconductor field effect transistor (MOSFET) having a drain, a gate, and a source;

a junction field effect transistor (JFET) having a drain, a gate, and a source, the source of the JFET being coupled to a drain sense terminal of the integrated circuit, the drain of the JFET being coupled to the drain of the power MOSFET and a drain terminal of the integrated circuit, the JFET and the power MOSFET sharing a same drift region on a substrate of the integrated circuit;

a source terminal of the integrated circuit coupled to the source of the power MOSFET; and

a gate terminal of the integrated circuit coupled to the gate of the power MOSFET.

2. The integrated circuit of claim 1, wherein the integrated circuit is packaged in a four terminal small outline integrated circuit (SOIC) package.

3. The integrated circuit of claim 1 wherein the integrated circuit only includes the JFET and the power MOSFET.

4. The integrated circuit of claim 1 wherein the JFET and the power MOSFET are vertical transistors, and configured to use the substrate of the integrated circuit as the drain.

5. The integrated circuit of claim 1 wherein the drift region of the JFET and the power MOSFET includes an epitaxial layer formed on the substrate.

6. The integrated circuit of claim 5 wherein the substrate comprises an N-type silicon substrate.

7. An integrated circuit comprising:

a power MOSFET;

a JFET sharing a same drift region with the power MOSFET on a same substrate;

a drain sense terminal coupled to a drain of the power MOSFET through the JFET, the drain sense terminal being external to a package of the integrated circuit and configured to allow an external circuit to sense the drain of the power MOSFET; and

a gate terminal coupled to a gate of the power MOSFET, the gate terminal being external to the package of the integrated circuit.

8. The integrated circuit of claim 7 wherein the power MOSFET and the JFET are vertical trench-gate transistors.

9. The integrated circuit of claim 7 wherein the package is a four terminal SOIC package.

10. The integrated circuit of claim 7 wherein the integrated circuit only includes the JFET and the power MOSFET.

11. The integrated circuit of claim 7 wherein the drift region comprises an epitaxial layer.