Method of forming a transistor and structure therefor

• US 8,723,238 B1
• Filed: 03/15/2013
• Issued: 05/13/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Venkatraman, Prasad, Grivna, Gordon M.
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US13/831,887
• Time in Patent Office: 424 Days
• Field of Search: 257/288, 257/330
• US Class Current: 257/288
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

In one embodiment, a semiconductor device is formed to include a gate structure extending into a first portion of a semiconductor material that is underlying a first region of semiconductor material. The gate structure separates a portion of the first region into at least a first current carrying electrode region and a second current carrying electrode region. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies a gate conductor of the gate structure. The gate structure also includes a shield conductor overlying the gate conductor and having a shield insulator positioned between the shield conductor and the gate conductor. The shield insulator also having a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Claims

1. A transistor comprising:

a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface;

a first semiconductor region of the first conductivity type on the first surface of the semiconductor substrate;

a second semiconductor region formed within the first semiconductor region wherein a first portion of the first semiconductor region underlies the second semiconductor region, the second semiconductor region having a second conductivity type;

a gate structure formed in an opening that extends from the second semiconductor region into the first portion of the first semiconductor region wherein the opening separates the second semiconductor region into a first current carrying electrode region and a second current carrying electrode region;

a gate conductor of the gate structure formed within the opening and overlying the first portion of the first semiconductor region wherein a first side of the first current carrying electrode region is adjacent one side of the gate conductor and spaced laterally from the gate conductor and the second current carrying electrode region is adjacent a different side of the gate conductor and spaced laterally from the gate conductor;

a shield conductor overlying the gate conductor; and

a shield insulator between the gate conductor and the shield conductor.

2. The transistor of claim 1 wherein the gate structure is devoid of a shield conductor underlying the gate conductor.

3. The transistor of claim 1 further including another gate structure adjacent an opposite side of the first current carrying electrode region so that a shield conductor is adjacent and spaced apart from each side of the first current carrying electrode region.

4. The transistor of claim 1 further including a gate insulator between the gate conductor and the first portion of the first semiconductor region wherein a channel region of the transistor is in the first semiconductor region that is underlying the gate conductor so that current flows laterally under the gate structure between the first current carrying electrode region and the second current carrying electrode region.

5. The transistor of claim 4 wherein a thickness of the gate insulator is less than a thickness of the shield insulator.

6. The transistor of claim 1 wherein a doping concentration of the substrate is greater than a doping concentration of the first semiconductor region.

7. The transistor of claim 1 wherein a doping concentration of the first current carrying electrode region is substantially equal to a doping concentration of the second current carrying electrode region.

8. The transistor of claim 1 wherein the gate insulator is abuts the shield insulator.

9. The transistor of claim 1 wherein the shield conductor is formed within an opening that is formed to extend into the shield insulator.

10. A semiconductor device comprising:

a semiconductor material of a first conductivity type having a first surface and a second surface;

a first region of the semiconductor material having a second conductivity type;

a gate structure extending into the semiconductor material that is underlying the first region wherein the gate structure forms the first region into a first current carrying electrode region and a second current carrying electrode region and wherein a doping concentration of the first current carrying electrode region is substantially equal to a doping concentration of the second current carrying electrode region;

a gate conductor of the gate structure overlying at least a first portion of the semiconductor material;

a gate insulator of the gate structure having a first portion of the gate insulator positioned between the gate conductor and the first portion of the semiconductor material that underlies the gate conductor wherein the first portion of the semiconductor material is configured to form a channel region of the transistor;

a shield conductor of the gate structure overlying the gate conductor;

a shield insulator having a first portion positioned between the shield conductor and the gate conductor, the shield insulator having a second portion positioned between the shield conductor and a second portion of the gate insulator.

11. The semiconductor device of claim 10 wherein the gate structure includes an opening extending from a surface of the first region into the semiconductor material with the gate insulator positioned on a bottom of the opening and the gate conductor within the opening and on the gate insulator.

12. The semiconductor device of claim 11 wherein a second portion of the gate insulator is positioned along a sidewall of the opening and abutting the shield insulator.

13. The semiconductor device of claim 11 wherein the shield conductor is within the opening and overlying the gate conductor.

14. The semiconductor device of claim 10 wherein a body region of the semiconductor device is not electrically connected to either the first current carrying electrode region or the second current carrying electrode region.

15. A method of forming a semiconductor device comprising:

providing a multi-layer semiconductor material having a first layer of a first conductivity type, having a first region of a second conductivity type overlying the first layer, having a plurality of openings that extend from a surface of the first region into the first layer wherein the plurality of openings have sidewalls, a gate insulator formed on the sidewalls of a first opening of the plurality of openings, and a gate conductor material within the first opening, and wherein the plurality of openings divide the first region into a first current carrying electrode region and a second current carrying electrode region;

forming a doping concentration of the first current carrying electrode region to be substantially equal to a doping concentration of the second current carrying electrode region;

forming the gate conductor material in the first opening into a gate conductor wherein a portion of the first layer that underlies the gate conductor forms a channel region of the semiconductor device;

forming a shield insulator within the first opening and overlying the gate conductor;

forming a shield conductor overlying the gate conductor; and

forming a source conductor on a portion of the shield conductor to form an electrical connection between the shield conductor and the first layer.

16. The method of claim 15 wherein providing the multi-layer semiconductor material includes providing a semiconductor substrate of the first conductivity type and forming the first layer on a first surface of the semiconductor substrate.

17. The method of claim 16 further including providing the semiconductor substrate with a first doping concentration and forming the first layer with a doping concentration that is lower than the first doping concentration.

18. The method of claim 16 further including forming a body conductor on a second surface of the semiconductor substrate.

19. The method of claim 15 wherein providing the multi-layer semiconductor material includes forming the plurality of openings to extend from a surface of the first layer into the first layer, then doping a portion of the first layer to form the first region with the first opening within the first region.

20. The method of claim 15 wherein forming the shield insulator within the first opening includes forming the shield insulator with a second opening within the shield insulator with at least a portion of the second opening extending substantially parallel to the sidewalls of the first opening, and forming the shield conductor within at least a portion of the second opening.