Nonvolatile semiconductor memory and manufacturing method thereof

• US 8,723,246 B2
• Filed: 06/04/2012
• Issued: 05/13/2014
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yaegashi, Toshitake
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Niesz, Jamie C
• Application Number:
  US13/487,342
• Publication Number:
  US 20120238087A1
• Time in Patent Office: 708 Days
• Field of Search: 257/316, 257/390, 257/E29.17
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.

Claims

1. A nonvolatile semiconductor memory comprising:

at least one memory cell disposed on a semiconductor substrate,

the memory cell having;

a first gate insulating film provided on a first element area of the semiconductor substrate, the first element area being defined by a first isolation insulating layer provided on the semiconductor substrate;

a charge storage layer provided on the first gate insulating film;

a first intergate insulating film having a multilayer structure and provided on the charge storage layer and the first isolation insulating layer; and

a control gate electrode provided on the first intergate insulating film; and

a peripheral transistor having;

a second gate insulating film provided on a second element area of the semiconductor substrate, the second element area being defined by a second isolation insulating layer provided on the semiconductor substrate;

a first gate electrode provided on the second gate insulating film and having a width larger than that of the charge storage layer;

a second intergate insulating film having a multilayer structure and provided on the first gate electrode and the second isolation insulating layer; and

a second gate electrode provided on the second intergate insulating film,

wherein the first intergate insulating film has n (n is natural number) layers on the charge storage layer and has m layers (m is natural number and m<

n) on the first isolation insulating layer, and

wherein the second intergate insulating film has n layers on the first gate electrode and an entire portion between the second isolation insulating layer and the second gate electrode in a direction perpendicular to a surface of the semiconductor substrate.

2. The nonvolatile semiconductor memory according to claim 1, wherein the first intergate insulating film includes a first portion disposed on an upper surface of the charge storage layer, a second portion disposed on the first isolation insulating layer, and a third portion disposed on a side surface of the charge storage layer,

wherein a thickness of the third portion is larger than that of the first and second portion in a direction perpendicular to the surface of the semiconductor substrate.

3. The nonvolatile semiconductor memory according to claim 2, wherein the third portion has n layers.

4. The nonvolatile semiconductor memory according to claim 1, wherein the first intergate insulating film includes a first portion contacting an upper surface of the charge storage layer, a second portion contacting an upper surface of the first isolation insulating layer, and a third portion contacting a side surface of the charge storage layer,

wherein the first portion has n layers and the second portion has m layers.

5. The nonvolatile semiconductor memory according to claim 4, wherein a thickness of the third portion is larger than that of the first and second portions in a direction perpendicular to a surface of the semiconductor substrate.

6. The nonvolatile semiconductor memory according to claim 4, wherein the third portion has n layers.

7. The nonvolatile semiconductor memory according to claim 1, wherein m is equal to n−

1.

8. The nonvolatile semiconductor memory according to claim 1, wherein the second intergate insulating film includes a first portion disposed on the first gate electrode, a second portion disposed on an upper surface of the second isolation insulating layer, and a third portion disposed on a side surface of the second gate electrode,

wherein the first portion and the second portion have n layers.

9. The nonvolatile semiconductor memory according to claim 8, wherein the third portion has n layers.

10. The nonvolatile semiconductor memory according to claim 1, wherein the second intergate insulating film includes a first portion contacting an upper surface of the first gate electrode, a second portion contacting an upper surface of the second isolation insulating layer, and a third portion contacting a side surface of the second isolation insulating layer,

wherein the first portion and the second portion have n layers.

11. The nonvolatile semiconductor memory according to claim 10, wherein a thickness of the third portion is larger than that of the first and second portions in a direction perpendicular to a surface of the semiconductor substrate.

12. The nonvolatile semiconductor memory according to claim 10, wherein the third portion has n layers.

13. The nonvolatile semiconductor memory according to claim 1, wherein m is equal to n−

1.

14. The nonvolatile semiconductor memory according to claim 1, wherein a thickness at an end of an insulating film serving as a lowermost layer of the second intergate insulating film contacting to the second isolation insulating layer is smaller than a thickness in a center of the insulating film serving as the lowermost layer of the second intergate insulating film contacting the second isolation insulating layer.

15. The nonvolatile semiconductor memory according to claim 1, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and silicon oxide films.

16. The nonvolatile semiconductor memory according to claim 1, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and high dielectric films.