Semiconductor device and manufacturing method thereof

• US 8,723,254 B2
• Filed: 06/29/2010
• Issued: 05/13/2014
• Est. Priority Date: 10/26/2009
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Hikichi, Toshiaki
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): TAYLOR, EARL N
• Application Number:
  US12/825,972
• Publication Number:
  US 20110095302A1
• Time in Patent Office: 1,414 Days
• Field of Search: 257/331, 257/332
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type formed in a surface portion of said first semiconductor layer on one thickness direction side;

a third semiconductor layer of the first conductivity type selectively formed in a surface portion of said second semiconductor layer on the one thickness direction side;

a gate electrode buried in a gate trench passing through said second and third semiconductor layers to reach said first semiconductor layer, with a gate insulating film interposed therebetween;

a fourth semiconductor layer of the second conductivity type formed in a portion of said second semiconductor layer, the fourth semiconductor layer forming a bottom of a contact trench, the contact trench passing through said third semiconductor layer to reach said second semiconductor layer, said fourth semiconductor layer having a higher concentration of the second conductivity type impurity than said second semiconductor layer, said fourth semiconductor layer and said first conductor layer interfacing along a horizontal plane surface, and said second semiconductor layer and said third semiconductor layer interfacing along the same horizontal plane surface; and

a contact electrode buried in said contact trench and in contact with said third and fourth semiconductor layers,

said gate electrode including;

an internal gate electrode buried in a part of said gate trench including its bottom; and

a low-resistance gate electrode buried in a remaining part of said gate trench and in contact with said internal gate electrode, said low-resistance gate electrode having a lower resistance than said internal gate electrode, and

said contact electrode including;

a first conductor layer buried in said contact trench; and

a second conductor layer that is in contact with said first conductor layer and covers said third semiconductor layer and said gate electrode with an interlayer insulating film interposed therebetween,

said first conductor layer and said second conductor layer being made of different materials, and

said low-resistance gate electrode and said first conductor layer being made of a same material.

2. The semiconductor device according to claim 1, wherein said low-resistance gate electrode is in contact with said internal gate electrode in a plane that is located to the side of said third semiconductor layer away from an interface between said third semiconductor layer and said second semiconductor layer.

3. The semiconductor device according to claim 1, which is a MOS field effect transistor in which said contact electrode is a source electrode and which comprises a drain electrode on the other thickness direction side of said first semiconductor layer.

4. The semiconductor device according to claim 1, which is an insulated gate bipolar transistor in which said contact electrode is an emitter electrode and which comprises a fifth semiconductor layer of the second conductivity type and a collector electrode on the other thickness direction side of said first semiconductor layer.

5. The semiconductor device according to claim 1, wherein said first to fourth semiconductor layers are formed of silicon carbide.

6. The semiconductor device according to claim 1, wherein a bottom of said contact trench is formed by said fourth semiconductor layer, and a side of said contact trench is formed by said third semiconductor layer.

7. The semiconductor device according to claim 1, wherein said internal gate electrode is filled at a whole bottom of said gate trench.

8. The semiconductor device according to claim 1, wherein the contact trench is formed to reach the second semiconductor layer passing through the third semiconductor layer from openings of the interlayer insulating film.