FinFET device and method of manufacturing same

• US 8,723,272 B2
• Filed: 10/04/2011
• Issued: 05/13/2014
• Est. Priority Date: 10/04/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chi-Wen, Wang, Chao-Hsiung
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Choi, Nicholas J
• Application Number:
  US13/252,892
• Publication Number:
  US 20130082304A1
• Time in Patent Office: 952 Days
• Field of Search: 257/332
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Claims

1. A semiconductor device comprising:

a substrate including a fin structure disposed over the substrate, wherein the fin structure includes a plurality of fins;

an insulation material disposed on the substrate between the plurality of fins of the fin structure without being disposed under the fin structure;

a gate structure disposed on a portion of the fin structure and on a portion of the insulation material, wherein the gate structure traverses the plurality of fins of the fin structure; and

a source and drain feature formed from a material having a continuous and uninterrupted surface area, wherein the source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, the plurality of fins of the fin structure, and the gate structure.

2. The semiconductor device of claim 1 wherein the substrate is selected from the group consisting of bulk silicon and silicon-on-insulator (SOI).

3. The semiconductor device of claim 1 wherein the gate structure includes a gate dielectric layer, a gate electrode disposed over the gate dielectric layer, and a gate spacer disposed on a sidewall of the gate electrode.

4. The semiconductor device of claim 1 wherein the semiconductor device is one of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device or a N-type metal-oxide-semiconductor (NMOS) FinFET device, and wherein the semiconductor device is included in an integrated circuit device.

5. The semiconductor device of claim 1 wherein the insulation material includes a surface at a second height (h2) upon which the gate structure is not disposed and a surface at a third height (h3) upon which the gate structure is disposed, the second height h2 being greater than the third height h3.

6. The semiconductor device of claim 1 wherein the source and drain feature includes a first height (h1) which is greater than a second height (h2) of the insulation material immediately adjacent to and in direct contact with the source and drain feature.

7. The semiconductor device of claim 3 wherein the source and drain feature is in direct contact with the substrate, the insulation material, the gate spacers. and each fin of the fin structure.

8. A semiconductor device comprising:

a substrate;

a fin structure including one or more fins disposed over the substrate, the fin structure including a first surface in a first common plane and a second surface in a second common plane, the first and second common planes being different;

a dielectric layer disposed on a central portion of the fin structure;

a gate electrode disposed on the dielectric layer, the gate electrode traversing the one or more fins and separating source and drain regions of the semiconductor device, the source and drain regions defining a channel region, for each of the one or more fins, therebetween;

a first gate spacer formed on a first sidewall of the gate electrode and a second gate spacer formed on a second sidewall of the gate electrode, the first gate spacer including a surface in the first common plane and the second gate spacer including a surface in the second common plane;

strained source and drain features formed directly on the substrate in the source and drain regions, the strained source and drain features being formed from a material having a continuous and uninterrupted surface area; and

an insulation material disposed on the substrate between the one or more fins of the fin structure without being disposed under the fin structure, the insulation material including a first surface in the first common plane and a second surface in the second common plane,

wherein the strained source and drain features include;

a first surface that is in direct contact with and parallel to the first surface of fin structure, the first surface of the insulation material, and the surface of the first gate spacer, in the first common plane, and

a second surface that is in direct contact with and parallel to the second surface of the fin structure, the second surface of the insulation material, and the surface of the second gate spacer, in the second common plane.

9. The semiconductor device of claim 8 wherein the strained source and drain features include silicon germanium.

10. The semiconductor device of claim 8 wherein the first common plane and the second common plane are substantially parallel.

11. The semiconductor device of claim 8 wherein the semiconductor substrate and the fin structure include silicon.

12. A semiconductor device comprising:

a substrate including a fin structure disposed over the substrate, wherein the fin structure includes more than one fin;

an insulation material disposed on the substrate;

a gate dielectric distinct from the insulation material and disposed on a portion of the fin structure and on a portion of the insulation material, wherein the gate dielectric traverses each fin of the fin structure;

a gate electrode disposed on the gate dielectric, wherein the gate structure traverses each fin of the fin structure;

a gate spacer disposed on a sidewall of the gate electrode; and

a source and drain feature formed from a material having a continuous and uninterrupted surface area, wherein the source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each fin of the fin structure. the gate dielectric, and the gate spacer.

13. The semiconductor device of claim 12 wherein the substrate is selected from the group consisting of bulk silicon and silicon-on-insulator (SOI).

14. The semiconductor device of claim 12 wherein the semiconductor device is one of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device or a N-type metal-oxide-semiconductor (NMOS) FinFET device, and wherein the semiconductor device is included in an integrated circuit device.

15. The semiconductor device of claim 12 wherein the insulation material includes a surface at a second height (h2) upon which the gate dielectric is not disposed and a surface at a third height (h3) upon which the gate dielectric is disposed, the second height h2 being greater than the third height h3.

16. The semiconductor device of claim 12 wherein the source and drain feature includes a first height (h1) which is greater than a second height (h2) of the insulation material immediately adjacent to and in direct contact with the source and drain feature.