Semiconductor circuit structure and method of forming the same using a capping layer

• US 8,723,335 B2
• Filed: 07/30/2010
• Issued: 05/13/2014
• Est. Priority Date: 05/20/2010
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US12/847,244
• Publication Number:
  US 20110285027A1
• Time in Patent Office: 1,383 Days
• Field of Search: 257/774, 257/773, 257/E23.011, 257/E21.09, 438/478, 438/637
• US Class Current: 257/781
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83138 the guiding structures being at least partially left in the finished device
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/92 Specific sequence of method steps
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor structure includes an interconnect region, and a material transfer region coupled to the interconnect region through a bonding interface. The semiconductor structure includes a capping layer sidewall portion which extends annularly around the material transfer region and covers the bonding interface. The capping layer sidewall portion restricts the flow of debris from the bonding interface.

Claims

1. A semiconductor structure, comprising:

an interconnect region;

a material transfer region coupled to the interconnect region through a bonding interface established by a conductive bonding layer; and

a capping layer sidewall portion which extends annularly around the material transfer region and covers the outer periphery of the bonding interface, the capping layer sidewall portion being adjacent to the conductive bonding layer and extending along an etched sidewall of the material transfer region, wherein the capping layer sidewall portion includes a dielectric material having a larger permittivity than the dielectric material of the interconnect region.

2. The structure of claim 1, wherein the capping layer sidewall portion consists of a dielectric material.

3. The structure of claim 1, wherein the interconnect region includes a conductive line which extends through a dielectric material region.

4. The structure of claim 3, further including a support substrate which carries the interconnect region and an electronic device in communication with the conductive line.

5. The structure of claim 3, wherein establishes the bonding interface, wherein the conductive bonding layer being is in communication with the conductive line.

6. The structure of claim 1, wherein the bonding interface is a metal-to-semiconductor bonding interface.

7. The structure of claim 1, wherein the capping layer sidewall portion extends adjacent to the interconnect region.

8. The structure of claim 1, wherein the capping layer sidewall portion extends adjacent to an outer periphery of the interconnect region.

9. The structure of claim 1, wherein the capping layer sidewall portion extends proximate to an outer periphery of the interconnect region and material transfer region.

10. The structure of claim 1, wherein the capping layer sidewall portion covers a lip of the interconnect region.

11. A semiconductor structure, comprising:

a support substrate which carries an electronic device;

an interconnect region carried by the support substrate, the interconnect region including a dielectric material and a conductive line in communication with the electronic device;

a conductive bonding layer coupled to the interconnect region, the conductive bonding layer being in communication with the conductive line;

a material transfer region coupled to the interconnect region through the conductive bonding layer; and

a capping layer sidewall portion which extends annularly around the conductive bonding layer, the capping layer sidewall portion being adjacent to the conductive bonding layer and extending along an etched sidewall of the material transfer region, wherein the capping layer sidewall portion includes a dielectric material having a larger permittivity than the dielectric material of the interconnect region.

12. The structure of claim 11, wherein the material transfer region includes a dielectric material region.

13. The structure of claim 11, wherein the material transfer region includes a semiconductor material region.

14. The structure of claim 11, wherein the material transfer region includes a single crystalline semiconductor material region.

15. The structure of claim 11, wherein the material transfer region includes a stack of single crystalline semiconductor material layers.

16. The structure of claim 11, wherein the dielectric material of the capping layer sidewall portion having a larger permittivity than the material of the material transfer region.

17. The structure of claim 11, wherein the conductive line extends through the dielectric material of the interconnect region.