Autonomous controlled headroom low dropout regulator for single inductor multiple output power supply

• US 8,723,492 B2
• Filed: 03/22/2011
• Issued: 05/13/2014
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Korzeniowski, Kenneth A.
• Primary Examiner(s): Han, Jessica
• Application Number:
  US13/069,329
• Publication Number:
  US 20120242309A1
• Time in Patent Office: 1,148 Days
• Field of Search: 323267-277, 323280-290
• US Class Current: 323/273
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A controlled headroom low dropout regulator (CHLDO) having an LDO with an input voltage provided by a capacitor. An incremental voltage is added to an output voltage of the LDO to create a reference voltage. The reference voltage is compared to the input voltage to determine when to couple/de-couple the capacitor with a current source. If the capacitor is coupled to the current source, the capacitor will charge only if the voltage driven by the current source exceeds the input voltage provided by the capacitor. When the input voltage developed on the capacitor exceeds the reference voltage, the capacitor is automatically de-coupled from the current source. Multiple CHLDOs can be charged from a single current source, wherein charging automatically proceeds from the lowest voltage CHLDO to the highest voltage CHLDO.

Claims

1. A controlled headroom low dropout regulator (CHLDO) comprising:

a low dropout regulator (LDO) having an input terminal and an output terminal, wherein an output voltage (V_OUT_P) of the CHLDO is provided on the output terminal of the LDO;

a capacitor (C1) coupled to the input terminal of the LDO;

a voltage source that adds an incremental voltage (V_DIFF) to the output voltage of the CHLDO, thereby providing a reference voltage (V_REF);

a comparator having a first input terminal coupled to receive the reference voltage and a second input terminal coupled to receive an input voltage (V_IN_P) from the input terminal of the LDO, wherein the comparator exhibits a hysteresis voltage V_H;

a current input terminal I_POS that receives an input current;

a switch coupled between the current input terminal and the input terminal of the LDO, the switch having a control terminal coupled to an output terminal of the comparator, wherein the switch is turned on when the input voltage of the LDO is less than the reference voltage by more than the hysteresis voltage, and wherein the switch is turned off when the input voltage of the LDO is greater than the reference voltage.

2. The CHLDO of claim 1, wherein the incremental voltage is 0.3 Volts or less.

3. The CHLDO of claim 1, wherein the LDO has a specified minimum voltage on the input terminal, wherein the reference voltage minus the hysteresis voltage is greater than the specified minimum voltage.

4. The CHLDO of claim 1, wherein the incremental voltage is 15 percent or less of the output voltage of the CHLDO.

5. The CHLDO of claim 1, further comprising a rectifier diode connected between the current input terminal and the switch, thereby inhibiting current flow from the capacitor to the current input terminal.

6. The CHLDO of claim 1, further comprising a bias voltage terminal (V_POS) that supplies a bias voltage, wherein the bias voltage terminal is coupled to the voltage supply, and wherein the bias voltage is greater than the output voltage of the CHLDO.

7. A controlled headroom low dropout regulator (CHLDO) comprising:

a low dropout regulator (LDO) having an input terminal and an output terminal, wherein an output voltage (V_OUT_P) of the CHLDO is provided on the output terminal of the LDO;

a capacitor (C1) coupled to the input terminal of the LDO;

a voltage source that adds an incremental voltage (V_DIFF) to the output voltage of the CHLDO, thereby providing a reference voltage (V_REF);

a comparator having a first input terminal coupled to receive the reference voltage and a second input terminal coupled to receive an input voltage (V_IN_P) from the input terminal of the LDO;

a current input terminal I_POS that receives an input current;

a clock input terminal that receives a clock signal;

a switch coupled between the current input terminal and the input terminal of the LDO;

sequential logic coupled to the clock input terminal, an output of the comparator and the switch, wherein the sequential logic enables the switch at a first edge of the clock signal, and disables the switch after a second edge of the clock signal, when the input voltage exceeds the reference voltage.

8. The CHLDO of claim 7, wherein the incremental voltage is 0.3 Volts or less.

9. The CHLDO of claim 7, wherein the incremental voltage is 15 percent or less of the output voltage of the CHLDO.

10. The CHLDO of claim 7, further comprising a rectifier diode connected between the current input terminal and the switch, thereby inhibiting current flow from the capacitor to the current input terminal.

11. The CHLDO of claim 7, further comprising a bias voltage terminal (V_POS) that supplies a bias voltage, wherein the bias voltage terminal is coupled to the voltage supply, and wherein the bias voltage is greater than the output voltage of the CHLDO.

12. The CHLDO of claim 7, wherein the sequential logic comprises:

a logical AND gate having a first input terminal coupled to the output of the comparator and a second input terminal coupled to the clock input terminal; and

a reset-set flip-flop having a set input terminal coupled to the clock input terminal, a reset input terminal coupled to an output of the logical AND gate, and an output terminal coupled to the control terminal of the switch.

13. A method of operating a low dropout regulator (LDO) comprising:

supplying an input voltage of the LDO from a capacitor;

adding an incremental voltage to an output voltage of the LDO to create a reference voltage;

comparing the reference voltage with the input voltage of the LDO, and in response, generating a switch control signal (Q1);

coupling the capacitor to a current supply terminal if the input voltage of the LDO becomes less than the reference voltage by a hysteresis voltage; and

de-coupling the capacitor from the current supply terminal if the input voltage of the LDO is greater than the reference voltage.

14. The method of claim 13, wherein the incremental voltage is 0.3 Volts or less.

15. The method of claim 13, wherein the LDO has a specified minimum voltage on the input terminal, wherein the reference voltage minus the hysteresis voltage is greater than the specified minimum voltage.

16. The method of claim 13, wherein the incremental voltage is 15 percent or less of the output voltage of the CHLDO.

17. The method of claim 13, further comprising generating the incremental voltage in response to a bias voltage, wherein the bias voltage is greater than the output voltage of the LDO.

18. A method of operating a low dropout regulator (LDO) comprising:

supplying an input voltage of the LDO from a capacitor;

adding an incremental voltage to an output voltage of the LDO to create a reference voltage;

comparing the reference voltage with the input voltage of the LDO, and in response, generating a switch control signal (Q1);

coupling the capacitor to a current supply terminal in response to a first edge of a clock signal; and

de-coupling the capacitor from the current supply terminal in response to the input voltage of the LDO becoming greater than the reference voltage after a second edge of the clock signal.

19. The method of claim 18, wherein the incremental voltage is 0.3 Volts or less.

20. The method of claim 18, wherein the incremental voltage is 15 percent or less of the output voltage of the CHLDO.

21. The method of claim 18, further comprising generating the incremental voltage in response to a bias voltage, wherein the bias voltage is greater than the output voltage of the LDO.

22. A single-inductor multiple output (SIMO) power supply comprising:

an inductor;

a control circuit that charges the inductor during a first phase of a clock signal and discharges the inductor during a second phase of the clock signal;

a first plurality of controlled overhead low dropout regulators (CHLDOs), each having a corresponding rectifier coupled to the inductor, each having a corresponding capacitor for providing an input voltage, and each having means for coupling the corresponding capacitor to the corresponding rectifier during the first phase of the clock signal, and means for de-coupling the corresponding capacitor from the corresponding rectifier during the second phase of the clock signal when a voltage developed on the corresponding capacitor becomes greater than a predetermined reference voltage assigned to the CHLDO.

23. The SIMO power supply of claim 22, wherein each of the CHLDOs has a different predetermined reference voltage.

24. The SIMO power supply of claim 23, wherein each predetermined reference voltage is a positive voltage.

25. The SIMO power supply of claim 22, further comprising a second plurality of controlled overhead low dropout regulators (CHLDOs), each having a corresponding rectifier coupled to the inductor, each having a corresponding capacitor for providing an input voltage, and each having means for coupling the corresponding capacitor to the corresponding rectifier during the first phase of the clock signal, and means for de-coupling the corresponding capacitor from the corresponding rectifier during the second phase of the clock signal when a voltage developed on the corresponding capacitor becomes less than a predetermined reference voltage assigned to the CHLDO.

26. The SIMO power supply of claim 25, wherein the first plurality of CHLDOs are coupled to a first terminal of the inductor, and the second set of CHLDOs are coupled to a second terminal of the inductor.

27. The SIMO power supply of claim 25, wherein the predetermined reference voltages of the first plurality of CHLDOs are positive voltages, and the predetermined reference voltages of the second plurality of CHLDOs are negative voltages.

28. The SIMO power supply of claim 25, wherein the control circuit includes:

a supply capacitor that is charged to a predetermined negative voltage to supply the second plurality of CHLDOs; and

a switch that is maintained in a first state until the supply capacitor is charged to the predetermined negative voltage, and is switched to a second state in response to the supply capacitor charging to the predetermined negative voltage, wherein the supply capacitor is prevented from charging when the switch is in the second state.

29. The SIMO power supply of claim 22, wherein the control circuit is of a Buck controller type.

30. The SIMO power supply of claim 22, wherein the control circuit is of a Boost controller type.

31. The SIMO power supply of claim 22, wherein the control circuit is of a Buck-Boost controller type.

32. The SIMO power supply of claim 22, wherein the control circuit includes means for charging a capacitor to create a bias voltage, and wherein each of the CHLDOs further comprises means for creating the corresponding predetermined reference voltage in response to the bias voltage.