Level shifter circuit

• US 8,723,582 B1
• Filed: 02/19/2013
• Issued: 05/13/2014
• Est. Priority Date: 02/19/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Goyal, Gaurav, Gupta, Gaurav, Malhan, Bipin B.
• Primary Examiner(s): Nguyen, Long
• Application Number:
  US13/771,025
• Time in Patent Office: 448 Days
• Field of Search: 327/112, 327/333, 327/427, 326/68, 326/80, 326/81, 365/189.11
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00 Logic circuits, i.e. having at least two inputs acting on one output circuits for computer systems using fuzzy logic G06N7/02; Inverting circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

A single supply level shifter circuit for shifting the voltage level of an input voltage includes a voltage translation stage and a driver stage. The voltage translation stage receives the input voltage and a voltage supply and generates a first voltage. When a magnitude of the input voltage is LOW, the first voltage is LOW. The first voltage is provided to the driver stage, which inverts the first voltage to generate an output voltage that is at a voltage supply (Vdd) level, thereby level shifting the input voltage.

Claims

1. A level shifter circuit for generating an output voltage based on an input voltage, comprising:

a voltage translation stage for receiving the input voltage, comprising;

a first transistor having a source terminal for receiving a voltage supply;

a second transistor having a drain terminal connected to a drain terminal of the first transistor, a gate terminal for receiving the input voltage, and a source terminal connected to ground;

a third transistor having a source terminal for receiving the voltage supply, and a gate terminal connected to the drain terminals of the first and second transistors; and

a fourth transistor having a drain terminal connected to a drain terminal of the third transistor and a gate terminal of the first transistor, and a source terminal connected to ground;

a driver stage connected to the voltage translation stage for generating the output voltage; and

a comparison stage, connected to the voltage translation stage, comprising;

a fifth transistor having a source terminal connected to the drain terminals of the first and second transistors, and a drain terminal connected to a gate terminal of the fourth transistor;

a sixth transistor having a drain terminal connected to the source terminal of the fifth transistor, a gate terminal for receiving the input voltage, and a source terminal connected to the drain terminal of the fifth transistor;

a seventh transistor having a source terminal connected to the drain terminals of the third and fourth transistors, a drain terminal connected to the drain and source terminals of the fifth and sixth transistors, respectively, and a gate terminal connected to the gate terminal of the sixth transistor for receiving the input voltage; and

an eighth transistor having a drain terminal connected to the source terminal of the seventh transistor, a gate terminal connected to a gate terminal of the fifth transistor and the drain terminals of the first and second transistors, and a source terminal connected to the drain terminal of the seventh transistor.

2. The level shifter circuit of claim 1, wherein the driver stage includes:

a ninth transistor having a gate terminal connected to the drain terminals of the first and second transistors, and a source terminal for receiving the voltage supply; and

a tenth transistor having a drain terminal connected to a drain terminal of the ninth transistor, a gate terminal connected to the gate terminal of the ninth transistor, and a source terminal connected to ground, wherein the output voltage is generated at the drain terminals of the ninth and tenth transistors.

3. The level shifter circuit of claim 2, wherein the first, third, fifth, seventh, and ninth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

4. The level shifter circuit of claim 3, wherein the second, fourth, sixth, eighth, and tenth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.

5. A level shifter circuit for generating an output voltage based on an input voltage, comprising:

a voltage translation stage for receiving the input voltage, comprising;

a first transistor having a source terminal for receiving a voltage supply;

a second transistor having a drain terminal connected to a drain terminal of the first transistor, a gate terminal for receiving the input voltage, and a source terminal connected to ground;

a third transistor having a source terminal for receiving the first voltage supply, and a gate terminal connected to the drain terminals of the first and second transistors; and

a fourth transistor having a drain terminal connected to a drain terminal of the third transistor and a gate terminal of the first transistor, and a source terminal connected to ground;

a driver stage connected to the voltage translation stage for generating the output voltage, comprising;

a fifth transistor having a gate terminal connected to the drain terminals of the first and second transistors, a source terminal for receiving the voltage supply; and

a sixth transistor having a drain terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to the gate terminal of the fifth transistor, and a source terminal connected to ground, wherein the output voltage is generated at the drain terminals of the fifth and sixth transistors; and

a comparison stage, connected to the voltage translation stage, comprising;

a seventh transistor having a source terminal connected to the drain terminals of the first and second transistors, and a drain terminal connected to a gate terminal of the fourth transistor;

an eighth transistor having a drain terminal connected to the source terminal of the seventh transistor, a gate terminal for receiving the input voltage, and a source terminal connected to the drain terminal of the seventh transistor;

a ninth transistor having a source terminal connected to the drain terminals of the third and fourth transistors, a drain terminal connected to the drain and source terminals of the seventh and eighth transistors, respectively, and a gate terminal connected to the gate terminal of the eighth transistor for receiving the input voltage; and

a tenth transistor having a drain terminal connected to the source terminal of the ninth transistor, a gate terminal connected to the gate terminal of the seventh transistor and the drain terminals of the first and second transistors, and a source terminal connected to the drain terminal of the ninth transistor.