Flat panel display apparatus
First Claim
Patent Images
1. A flat panel display apparatus, comprising:
- a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region including a first transistor and a first capacitor, and the first pixel region being covered by a first pixel electrode;
a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode;
the first gate line extending in a first direction, the first gate line being positioned between the first pixel electrode and the second pixel electrode;
a second capacitor included in the second pixel region, the second capacitor including a first transparent conductive layer and a second transparent conductive layer;
a transparent shielding portion extending from the second transparent conductive layer of the second capacitor toward the first pixel region, the transparent shielding portion covering two opposite edges of the first gate line between the first pixel electrode and the second pixel electrode; and
a second transistor in the second pixel region and connected to the second pixel electrode, the second transistor including;
a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region,a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the second gate line, anda source electrode and a drain electrode of the second transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode,wherein the second capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer, andwherein;
the first transparent conductive layer is on the capacitor wiring line,the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer, andthe second transparent conductive layer is connected to one of the source electrode and the drain electrode of the second transistor.
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Abstract
A flat panel display apparatus includes a first pixel region on a substrate and defined by an intersection between a first gate line and a data line. The first pixel region includes a first transistor and a first capacitor and is covered by a first pixel electrode. The apparatus includes a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line. The second pixel region is covered by a second pixel electrode. The first gate line is positioned between the first pixel electrode and the second pixel electrode. A second capacitor is in the second pixel region, and the second capacitor includes a first transparent conductive layer and a second transparent conductive layer. A transparent shielding portion extends from the second transparent conductive layer of the second capacitor toward the first pixel region to overlap with the first gate line.
5 Citations
15 Claims
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1. A flat panel display apparatus, comprising:
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a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region including a first transistor and a first capacitor, and the first pixel region being covered by a first pixel electrode; a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode; the first gate line extending in a first direction, the first gate line being positioned between the first pixel electrode and the second pixel electrode; a second capacitor included in the second pixel region, the second capacitor including a first transparent conductive layer and a second transparent conductive layer; a transparent shielding portion extending from the second transparent conductive layer of the second capacitor toward the first pixel region, the transparent shielding portion covering two opposite edges of the first gate line between the first pixel electrode and the second pixel electrode; and a second transistor in the second pixel region and connected to the second pixel electrode, the second transistor including; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region, a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the second gate line, and a source electrode and a drain electrode of the second transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode, wherein the second capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer, and wherein; the first transparent conductive layer is on the capacitor wiring line, the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer, and the second transparent conductive layer is connected to one of the source electrode and the drain electrode of the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A flat panel display apparatus, comprising:
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a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region being covered by a first pixel electrode; a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode; the first gate line extending in a first direction, the first gate line being positioned between the first pixel electrode and the second pixel electrode; a first capacitor included in the first pixel region, the first capacitor including a first transparent conductive layer and a second transparent conductive layer; a transparent shielding portion extending from the second transparent conductive layer of the first capacitor toward the second pixel region, the transparent shielding portion covering two opposite edges of the first gate line between the first pixel electrode and the second pixel electrode; and a first transistor in the first pixel region and connected to the first pixel electrode, the first transistor including; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region, a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the first gate line, and a source electrode and a drain electrode of the first transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode, wherein the first capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer, and wherein; the first transparent conductive layer is on the capacitor wiring line, and the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer, and the second transparent conductive layer is connected to one of the source electrode and the drain electrode of the first transistor. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification
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Current AssigneeTCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
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Original AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
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InventorsZhan, Zhi-Feng, Tae, Seung-Gyu, Moon, Sung-Hoon, Kim, Deok-Hoi
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Primary Examiner(s)Moon, Seokyun
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Application NumberUS13/137,478Publication NumberTime in Patent Office998 DaysField of SearchNoneUS Class Current345/87CPC Class CodesG02F 1/136213 Storage capacitors associat...G02F 1/136218 Shield electrodesG06F 1/00 Details not covered by grou...G09G 3/36 using liquid crystalsH01L 27/1255 integrated with passive dev...
