nvSRAM with inverted recall
First Claim
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1. A process of operating a memory circuit comprising:
- storing in a STORE operation a logical state of a volatile memory cell in a nonvolatile memory cell;
recalling in a RECALL operation the logical state of the volatile memory cell from the nonvolatile memory cell; and
inverting an output of the volatile memory cell after every other RECALL operation following a STORE operation.
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Abstract
A RECALL process in a memory circuit includes RECALLing the state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.
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Citations
20 Claims
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1. A process of operating a memory circuit comprising:
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storing in a STORE operation a logical state of a volatile memory cell in a nonvolatile memory cell; recalling in a RECALL operation the logical state of the volatile memory cell from the nonvolatile memory cell; and inverting an output of the volatile memory cell after every other RECALL operation following a STORE operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An nvRAM circuit comprising:
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a volatile charge storage circuit and a nonvolatile charge storage circuit; and logic to set, during every other RECALL following a STORE, a logical state of the volatile charge storage circuit to the inverse of a logical state stored by the nonvolatile charge storage circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An nvRAM circuit comprising:
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an SRAM cell coupled to a nonvolatile charge storage circuit, the nonvolatile charge storage circuit comprising exactly one nonvolatile charge storage transistor; and logic to set, during a RECALL operation following a STORE operation, a logical state of the SRAM cell to the inverse of a logical state stored by the nonvolatile charge storage circuit, and to invert the output of the cell after every other RECALL operation following a STORE operation. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification