Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages

• US 8,724,387 B2
• Filed: 08/27/2010
• Issued: 05/13/2014
• Est. Priority Date: 10/22/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Steiner, Avi, Weingarten, Hanan
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US12/870,487
• Publication Number:
  US 20110096612A1
• Time in Patent Office: 1,355 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.33
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A system, method and computer readable medium for programming and reading flash memory cells. Respective first and second read operations may be performed while supplying respective first and second bias voltage to multiple flash memory cells, to provide respective first and second read results, where the first bias voltage may be higher then the second bias voltage, and providing a read outcome that may be responsive to the first read results and to the second read results. A programming method may include performing first and second programming operations while supplying respective first and second bias voltages to multiple flash memory cells. The programming method may further include performing the first programming operation while programming information mapped to a highest least significant bit positive lobe, and performing the second programming operation while programming information mapped to at least one other least significant bit positive lobe.

Claims

1. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the read unit is configured to provide the second read results by comparing a content of the multiple non-volatile memory cells to a first threshold set to zero, and to a second threshold that has a value between a lowest positive lobe and a second lower positive lobe of a threshold voltage distribution of the non-volatile memory cells.

2. The system according to claim 1, wherein the controller is configured to determine whether a single read operation per read attempt or a pair of read operations per read attempt is to be performed by the read unit;

and wherein the read unit is configured to perform the single read operation per read attempt or the pair of read operations per read attempt based on the determination of the controller.

3. The system according to claim 2 further comprising an error detection unit configured to evaluate an error level of the single read operation;

and

wherein the controller is configured to determine whether to perform the pair of read operations if the error level exceeds a predefined error threshold.

4. The system according to claim 1, further comprising a decoder configured to hard decode the read outcome.

5. The system according to claim 1, further comprising an error detection unit configured to evaluate an error level of the pair of read operations.

6. The system according to claim 1, wherein the controller is configured to determine a value of at least one bias voltage within a bias voltage valid range based on a retention test based estimation of a threshold voltage distribution of the multiple flash memory cells.

7. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the read unit is configured to locate a set of non-volatile memory cells that according to the first read results store a zero logic value and according to the second read results store a lowest positive lobe value associated with a lowest positive lobe of a threshold voltage distribution of the non-volatile memory cells; and

wherein the read unit is configured to provide a read outcome that associates a lowest positive lobe value with the set of memory non-volatile cells.

8. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit;

an error detection unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memo cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the error detection unit is configured to evaluate an error level of the pair of read operations;

wherein the controller is configured to determine, based on the error level of the pair of read operations, whether to perform the pair of read operations per read attempt or to perform soft decoding per each read attempt of the multiple memory cells.

9. The system according to claim 8, wherein the read unit is configured to perform more than a pair of read operations per read attempt to provide multiple read outcomes.

10. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the bias voltage unit is configured to provide different values of bias voltages during read attempts of different page types, and wherein read attempts of different types relate to different bits out of multiple bits per cell that are stored in each of the multiple flash memory cells.

11. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the bias voltage unit is configured to provide bias voltages of a first set of values when performing a most significant bit type read operation, and to provide bias voltages of a second set of values when performing a least significant bit type read operation.

12. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the controller is configured to program the multiple flash memory cells while the bias voltage unit supplies a bias voltage that differs from the first and the second bias voltages.

13. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the controller is configured to program the multiple flash memory cells while the bias voltage unit supplies a bias voltage that is lower than the first and the second bias voltages.

14. A system for reading flash memory cells, the system comprising:

multiple flash memory cells that are arranged in multiple columns and in multiple rows;

a bias voltage unit;

a read unit; and

a controller;

wherein the read unit is configured to;

perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and

provide to the controller a read outcome that is responsive to the first read results and to the second read results;

wherein the read unit is configured to perform multiple iterations of the first and the second read operations, while the bias voltage unit supplies different bias voltages during different iterations, to provide multiple read outcomes.

15. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while su e a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the steps of providing the second read results by comparing a content of the multiple non-volatile memory cells to a first threshold set to zero, and to a second threshold that has a value between a lowest positive lobe and a second lower positive lobe of a threshold voltage distribution of the non-volatile memory cells.

16. The non-transitory computer readable medium according to claim 15 wherein the executable computer-readable program code when executed by a computer processor performs the steps of determining whether a single read operation per read attempt or a pair of read operations per read attempt is to be performed;

and performing the single read operation per read attempt or the pair of read operations per read attempt based on the determining.

17. The non-transitory computer readable medium according to claim 15 wherein the executable computer-readable program code when executed by a computer processor performs the step of hard decoding the read outcome.

18. The non-transitory computer readable medium according to claim 15 wherein the executable computer-readable program code when executed by a computer processor performs the step of evaluating an error level of the pair of read operations.

19. The non-transitory computer readable medium according to claim 15 wherein the executable computer-readable program code when executed by a computer processor performs the steps of determining a value of at least one bias voltage within a bias voltage valid range based on a retention test based estimation of a threshold voltage distribution of the multiple flash memory cells.

20. The non-transitory computer readable medium according to claim 16 wherein the executable computer-readable program code when executed by a computer processor performs the steps of evaluating an error level of the single read operation;

and determining whether to perform the pair of read operations if the error level exceeds a predefined error threshold.

21. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the steps of locating a set of non-volatile memory cells that according to the first read results store a zero logic value and according to the second read results store a lowest positive lobe value associated with a lowest positive lobe of a threshold voltage distribution of the non-volatile memory cells; and

providing a read outcome that associates a lowest positive lobe value with the set of memory non-volatile cells.

22. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the step of evaluating an error level of the pair of read operations;

wherein the executable computer-readable program code when executed by a computer processor performs the step of determining, based on the error level of the pair of read operations, whether to perform the pair of read operations per read attempt or to perform soft decoding per each read attempt of the multiple memory cells.

23. The non-transitory computer readable medium according to claim 22 wherein the executable computer-readable program code when executed by a computer processor performs the step of performing more than a pair of read operations per read attempt to provide multiple read outcomes.

24. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying in a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the step of providing different values of bias voltages during read attempts of different page types, and wherein read attempts of different types relate to different bits out of multiple bits per cell that are stored in each of the multiple flash memory cells.

25. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the steps of providing bias voltages of a first set of values when performing a most significant bit type read operation, and providing bias voltages of a second set of values when performing a least significant bit type read operation.

26. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the step of programming the multiple flash memory cells while supplying a bias voltage that differs from the first and the second bias voltages.

27. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the step of programming the multiple flash memory cells while the bias voltage unit supplies a bias voltage that is lower than the first and the second bias voltages.

28. A non-transitory computer readable medium having stored thereon an executable computer-readable program code for reading flash memory cells that are arranged in multiple rows and multiple columns, the executable computer-readable program when executed by a computer processor performs the steps of:

performing a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while supplying a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row;

performing a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row and supplying to flash memory cells of the other rows a second bias voltage to the multiple flash memory cells to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage; and

providing a read outcome that is responsive to the first read results and to the second read results;

wherein the executable computer-readable program code when executed by a computer processor performs the step of performing multiple iterations of the first and the second read operations, while supplying different bias voltages during different iterations, to provide multiple read outcomes.