Signal processing circuit

• US 8,724,407 B2
• Filed: 03/23/2012
• Issued: 05/13/2014
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kobayashi, Hidetomo, Maehashi, Yukio
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/428,015
• Publication Number:
  US 20120243340A1
• Time in Patent Office: 781 Days
• Field of Search: 365/189.2, 365/230.03, 365/230.05, 365/233.11
• US Class Current: 365/189.2
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Claims

1. A signal processing circuit comprising:

an arithmetic portion;

a memory; and

a control portion for controlling the arithmetic portion and the memory,

wherein the control portion includes a set of a first volatile memory circuit and a first nonvolatile memory circuit for storing data held in the first volatile memory circuit,

wherein the memory includes a plurality of second nonvolatile memory circuits arranged in matrix,

wherein the first nonvolatile memory circuit and the plurality of second nonvolatile memory circuits each include a transistor comprising a channel formation region in an oxide semiconductor layer, and

wherein the first nonvolatile memory circuit and the plurality of second nonvolatile memory circuits each include a capacitor in which one of a pair of electrodes of the capacitor is electrically connected to a node which is set in a floating state when the transistor is turned off.

2. The signal processing circuit according to claim 1, wherein the other of the pair of electrodes of the capacitor included in the first nonvolatile memory circuit and the other of the pair of electrodes of the capacitor included in each of the plurality of second nonvolatile memory circuits are provided in common without being separated from each other and are provided so as to cover a transistor included in the arithmetic portion, the transistor included in the memory, and the transistor included in the control portion.

3. The signal processing circuit according to claim 1, wherein the oxide semiconductor layer includes a crystal region in an amorphous phase.

4. The signal processing circuit according to claim 1, wherein the oxide semiconductor layer comprises at least one of indium and gallium.

5. An electronic device including the signal processing circuit according to claim 1.

6. A signal processing circuit comprising:

an arithmetic portion;

a memory; and

a control portion for controlling the arithmetic portion and the memory,

wherein the control portion includes a set of a first volatile memory circuit and a first nonvolatile memory circuit for storing data held in the first volatile memory circuit,

wherein the memory includes a plurality of second nonvolatile memory circuits arranged in matrix,

wherein the arithmetic portion includes a set of a second volatile memory circuit and a third nonvolatile memory circuit for storing data held in the second volatile memory circuit,

wherein the first nonvolatile memory circuit, the plurality of second nonvolatile memory circuits, and the third nonvolatile memory circuit each include a transistor comprising a channel formation region in an oxide semiconductor layer, and

wherein the first nonvolatile memory circuit, the plurality of second nonvolatile memory circuits, and the third nonvolatile memory circuit each include a capacitor in which one of a pair of electrodes of the capacitor is electrically connected to a node which is set in a floating state when the transistor is turned off.

7. The signal processing circuit according to claim 6, wherein the other of the pair of electrodes of the capacitor included in the first nonvolatile memory circuit, the other of the pair of electrodes of the capacitor included in each of the plurality of second nonvolatile memory circuits, and the other of the pair of electrodes of the capacitor included in the third nonvolatile memory circuit are provided in common without being separated from each other and are provided so as to cover the transistor included in the arithmetic portion, the transistor included the memory, and the transistor included the control portion.

8. The signal processing circuit according to claim 6, wherein the oxide semiconductor layer includes a crystal region in an amorphous phase.

9. The signal processing circuit according to claim 6, wherein the oxide semiconductor layer comprises at least one of indium and gallium.

10. An electronic device including the signal processing circuit according to claim 6.

11. A signal processing circuit comprising:

an arithmetic portion;

a memory; and

a control portion for controlling the arithmetic portion and the memory,

wherein the control portion includes;

a decoder for decoding a command;

a register for storing data input to the arithmetic portion and data output from the arithmetic portion;

a control circuit for controlling the register and the arithmetic portion; and

a power supply circuit for controlling the supply of power supply voltage to at least one of the arithmetic portion, the control circuit, the register, and the memory,

wherein the memory includes a plurality of second nonvolatile memory circuits arranged in matrix,

wherein the register includes a set of a third volatile memory circuit and a fourth nonvolatile memory circuit for storing data held in the third volatile memory circuit,

wherein the control circuit includes a set of a fourth volatile memory circuit and a fifth nonvolatile memory circuit for storing data held in the fourth volatile memory circuit,

wherein the plurality of second nonvolatile memory circuits, the fourth nonvolatile memory circuit, and the fifth nonvolatile memory circuit each include a transistor comprising a channel formation region in an oxide semiconductor layer, and

wherein the plurality of second nonvolatile memory circuits, the fourth nonvolatile memory circuit, and the fifth nonvolatile memory circuit each include a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

12. The signal processing circuit, according to claim 11, wherein the other of the pair of electrodes of the capacitor included in each of the plurality of second nonvolatile memory circuits, the other of the pair of electrodes of the capacitor included in the fourth nonvolatile memory circuit, and the other of the pair of electrodes of the capacitor included in the fifth nonvolatile memory circuit are provided in common without being separated from each other and are provided so as to cover a transistor included in the arithmetic portion, the transistor included in the memory, and the transistors included in the control portion.

13. The signal processing circuit according to claim 11, wherein the oxide semiconductor layer includes a crystal region in an amorphous phase.

14. The signal processing circuit according to claim 11, wherein the oxide semiconductor layer comprises at least one of indium and gallium.

15. An electronic device including the signal processing circuit according to claim 11.

16. A signal processing circuit comprising:

an arithmetic portion;

a memory; and

a control portion for controlling the arithmetic portion and the memory,

wherein the control portion includes;

a decoder for decoding a command;

a register for storing data input to the arithmetic portion and data output from the arithmetic portion;

a control circuit for controlling the register and the arithmetic portion; and

a power supply circuit for controlling supply of power supply voltage to at least one of the arithmetic portion, the control circuit, the register, and the memory,

wherein the memory includes a plurality of second nonvolatile memory circuits arranged in matrix,

wherein the arithmetic portion includes a set of a second volatile memory circuit and a third nonvolatile memory circuit for storing data held in the second volatile memory circuit,

wherein the register includes a set of a third volatile memory circuit and a fourth nonvolatile memory circuit for storing data held in the third volatile memory circuit,

wherein the control circuit includes a set of a fourth volatile memory circuit and a fifth nonvolatile memory circuit for storing data held in the fourth volatile memory circuit,

wherein the plurality of second nonvolatile memory circuits, the third nonvolatile memory circuit, the fourth nonvolatile memory circuit, and the fifth nonvolatile memory circuit each include a transistor comprising a channel formation region in an oxide semiconductor layer, and

wherein the plurality of second nonvolatile memory circuits, the third nonvolatile memory circuit, the fourth nonvolatile memory circuit, and the fifth nonvolatile memory circuit each include a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

17. The signal processing circuit according to claim 16, the resister further comprises another fourth nonvolatile memory circuit provided for the third volatile memory circuit.

18. The signal processing circuit according to claim 16, wherein the other of the pair of electrodes of the capacitor included in each of the plurality of second nonvolatile memory circuits, the other of the pair of electrodes of the capacitor included in the third nonvolatile memory circuit, the other of the pair of electrodes of the capacitor included in the fourth nonvolatile memory circuit, and the other of the pair of electrodes of the capacitor included in the fifth nonvolatile memory circuit are provided in common without being separated from each other and are provided so as to cover the transistor included in the arithmetic portion, the transistor included in the memory, and the transistors included in the control portion.

19. The signal processing circuit according to claim 16, wherein the oxide semiconductor layer includes a crystal region in an amorphous phase.

20. The signal processing circuit according to claim 16, wherein the oxide semiconductor layer comprises at least one of indium and gallium.

21. An electronic device including the signal processing circuit according to claim 16.