System and method for charging back-up charge storage element for data storage device using spindle phase switching elements

• US 8,724,422 B1
• Filed: 02/29/2012
• Issued: 05/13/2014
• Est. Priority Date: 02/29/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Agness, John R., Laird, William K., Ung, Henry S.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/407,984
• Time in Patent Office: 804 Days
• Field of Search: 365/229, 365/226
• US Class Current: 365/229
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A data storage system is disclosed including a data storage device having a controller coupled to non-volatile semiconductor memory and a power device having a common power rail and first, second, and third spindle phase switching elements, the common power rail receiving an input voltage and providing power to the data storage device and the power device. The data storage system further includes an inductor coupled between outputs of the first and second spindle phase switching elements, and a charge storage element coupled between the second spindle phase switching element output and ground. The power device further includes control circuitry that controls the first and second spindle phase switching elements to generate boost output voltage for charging the charge storage element during a boost mode, the boost output voltage enabling the controller to perform a data operation in an event of an interruption of power to the data storage system.

Claims

1. A data storage system comprising:

a data storage device comprising a controller coupled to non-volatile semiconductor memory (NVSM);

a power device comprising a common power rail, first, second, and third spindle phase switching elements and control circuitry, the common power rail receiving an input voltage and providing power to the data storage device and the power device;

an inductor coupled between an output of the first and an output of the second spindle phase switching element; and

a charge storage element coupled between the output of the second spindle phase switching element and ground,

wherein the control circuitry is operable to control the first and second spindle phase switching elements to generate a boost output voltage for charging the charge storage element during a boost mode, the boost output voltage enabling the controller to perform a data operation in an event of an interruption of power to the data storage system.

2. The data storage system as recited in claim 1, wherein the boost mode is triggered when the input voltage is applied to the common power rail.

3. The data storage system as recited in claim 1, wherein the data storage system further comprises a switchover circuit, the switchover circuit operable to couple a primary power rail providing the input voltage to the common power rail and decouple the primary power rail from the common power rail and couple a secondary power rail providing the boost output voltage to the common power rail when the input voltage falls below a threshold level.

4. The data storage system as recited in claim 3, wherein the switchover circuit comprises a first switch for coupling the primary power rail to the common power rail and a second switch for coupling the secondary power rail to the common power rail, the switchover circuit further operable to decouple the primary power rail from the common power rail by opening the first switch when the second switch couples the secondary power rail to the common power rail.

5. The data storage system as recited in claim 3, wherein the power device further comprises sense logic operable to monitor the input voltage and cause the switchover circuit to couple the secondary power rail to the common power rail when the input voltage falls below the threshold level.

6. The data storage system as recited in claim 1, wherein the power device further comprises a boost switching regulator operable to provide a trickle charge to the charge storage element.

7. The data storage system as recited in claim 6, wherein the boost switching regulator is operable to provide the trickle charge to the charge storage element after the charge storage element has been charged to the boost output voltage.

8. The data storage system as recited in claim 1, wherein the control circuitry is further operable to enable the controller when the charge storage element has been charged to the boost output voltage.

9. The data storage system as recited in claim 1, wherein the control circuitry is further operable to enable the controller when the input voltage is above a threshold level.

10. The data storage system as recited in claim 1, wherein the control circuitry is further operable to send an I/O signal to the controller to notify the controller when the charge storage element has been charged to the boost output voltage.

11. The data storage system as recited in claim 1, wherein the power device further comprises a timer operable to enable the controller after the input voltage has been applied to the common power rail for a predetermined amount of time.

12. The data storage system as recited in claim 1, further comprising a voltage monitoring circuit coupled to the charge storage element, wherein the voltage monitoring circuit is operable to enable the controller when the charge storage element has been charged to the boost output voltage.

13. The data storage system as recited in claim 1, wherein the control circuitry is coupled to the charge storage element via a feedback line.

14. The data storage system as recited in claim 1, wherein the first spindle phase switching element comprises a first low side FET coupled to a first high side FET and the second spindle phase switching element comprises a second low side FET coupled to a second high side FET.

15. The data storage system as recited in claim 14, wherein during the boost mode the control circuitry is operable to control the first and second spindle phase switching elements to generate the boost output voltage by switching the first high side FET on, switching the first low side FET off, switching the second high side FET off, and switching the second low side FET on and off continuously.

16. The data storage system as recited in claim 15, wherein the second low side FET is switched on and off with a controlled duty cycle.

17. The data storage system as recited in claim 6, wherein the first, second, and third spindle phase switching elements, the control circuitry, and the boost switching regulator are situated on one integrated circuit (IC).

18. The data storage system as recited in claim 1, wherein the charge storage element comprises a plurality of capacitors coupled together in a parallel configuration.

19. The data storage system as recited in claim 18, wherein each of the plurality of capacitors is a ceramic capacitor.

20. The data storage system as recited in claim 1, further comprising a rectification block coupled between the output of the second spindle phase switching element and the charge storage element.

21. A method of operating a data storage system, the method comprising:

controlling first and second spindle phase switching elements of a data storage system to generate a boost output voltage for charging a charge storage element of the data storage system during a boost mode,

wherein the data storage system comprises;

a data storage device comprising a controller coupled to non-volatile semiconductor memory (NVSM);

a power device comprising a common power rail, the first and second spindle phase switching elements, a third spindle phase switching element, and control circuitry, the common power rail receiving an input voltage and providing power to the data storage device and the power device;

an inductor coupled between an output of the first spindle phase switching element and an output of the second spindle phase switching element; and

a charge storage element coupled between the output of the second spindle phase switching element and ground, and

wherein the boost output voltage enables the controller to perform a data operation in an event of an interruption of power to the data storage system.

22. The method as recited in claim 21, further comprising triggering the boost mode when the input voltage is applied to the common power rail.

23. The method as recited in claim 21, wherein the data storage system further comprises a switchover circuit, further comprising performing the following in the switchover circuit:

coupling a primary power rail providing the input voltage to the common power rail and decoupling the primary power rail from the common power rail; and

coupling a secondary power rail providing the boost output voltage to the common power rail when the input voltage falls below a threshold level.

24. The method as recited in claim 23, wherein the switchover circuit comprises a first switch for coupling the primary power rail to the common power rail and a second switch for coupling the secondary power rail to the primary power rail, further comprising performing the following in the switchover circuit:

decoupling the primary power rail from the common power rail by opening the first switch when the second switch couples the secondary power rail to the common power rail.

25. The method as recited in claim 23, wherein the power device further comprises sense logic, further comprising performing the following in the sense logic:

monitoring the input voltage and causing the switchover circuit to couple the secondary power rail to the common power rail when the input voltage falls below the threshold level.

26. The method as recited in claim 21, wherein the power device further comprises a boost switching regulator, further comprising performing the following in the boost switching regulator:

providing a trickle charge to the charge storage element.

27. The method as recited in claim 26, further comprising performing the following in the boost switching regulator:

providing the trickle charge to the charge storage element after the charge storage element has been charged to the boost output voltage.

28. The method as recited in claim 21, further comprising enabling the controller when the charge storage element has been charged to the boost output voltage.

29. The method as recited in claim 21, further comprising enabling the controller when the input voltage is above a threshold level.

30. The method as recited in claim 21, further comprising sending an I/O signal to the controller to notify the controller when the charge storage element has been charged to the boost output voltage.

31. The method as recited in claim 21, wherein the power device further comprises a timer, further comprising performing the following in the timer:

enabling the controller after the input voltage has been applied to the common power rail for a predetermined amount of time.

32. The method as recited in claim 21, wherein the data storage system further comprises a voltage monitoring circuit coupled to the charge storage element, further comprising performing the following in the voltage monitoring circuit:

enabling the controller when the charge storage element has been charged to the boost output voltage.

33. The method as recited in claim 21, wherein the control circuitry is coupled to the charge storage element via a feedback line.

34. The method as recited in claim 21, wherein the first spindle phase switching element comprises a first low side FET coupled to a first high side FET and the second spindle phase switching element comprises a second low side FET coupled to a second high side FET.

35. The method as recited in claim 34, further comprising controlling during the boost mode the first and second spindle phase switching elements to generate the boost output voltage by switching the first high side FET on, switching the first low side FET off, switching the second high side FET off, and switching the second low side FET on and off continuously.

36. The method as recited in claim 35, wherein the second low side FET is switched on and off with a controlled duty cycle.

37. The method as recited in claim 26, wherein the first, second, and third spindle phase switching elements, the control circuitry, and the boost switching regulator are situated on one integrated circuit (IC).

38. The method as recited in claim 21, wherein the charge storage element comprises a plurality of capacitors coupled together in a parallel configuration.

39. The method as recited in claim 38, wherein each of the plurality of capacitors is a ceramic capacitor.

40. The method as recited in claim 21, wherein the data storage system further comprises a rectification block coupled between the output of the second spindle phase switching element and the charge storage element.