Loopback configuration for bi-directional interfaces

• US 8,724,483 B2
• Filed: 10/22/2007
• Issued: 05/13/2014
• Est. Priority Date: 10/22/2007
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Ku, Ting Sheng, Newcomb, Russell, Wagner, Barry A., Shaikh, Ashfaq R., Simms, William B.
• Primary Examiner(s): Skripnikov, Alex
• Application Number:
  US11/977,092
• Publication Number:
  US 20090103443A1
• Time in Patent Office: 2,395 Days
• Field of Search: None
• US Class Current: 370/249
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back

Abstract

An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Claims

1. A bi-directional communication bus system comprising:

a first component;

a second component;

a first portion configured to communicate signals between said first component and said second component, wherein said first portion is operable to implement a first lane; and

a second portion configured to communicate signals between said first component and said second component, wherein said second portion is operable to implement a second lane; and

wherein said first and second portions are operable to implement a plurality of loopback configurations one configuration at a time for communicating signals between said first and second components, wherein a first loopback configuration of said plurality of loopback configurations comprises a contemporaneous communication of signals in a first direction over said first portion and in a second direction over said second portion in a first configuration setting, wherein a second loopback configuration of said plurality of loopback configurations comprises a contemporaneous communication of signals in said second direction over said first portion and in said first direction over said second portion, wherein said second component comprises an interface component operable to couple said first and second portions in a second configuration setting, and wherein said interface component is further operable to couple said first and second portions to an auxiliary interface.

2. The bi-directional communication bus system of claim 1, wherein said first component is a graphics processor, wherein said second component comprises a memory, and wherein said first and second portions comprise a memory interface.

3. The bi-directional communication bus system of claim 1, wherein said first component is a memory controller, wherein said second component comprises a memory, and wherein said first and second portions comprise a memory interface.

4. The bi-directional communication bus system of claim 1, wherein said interface component comprises logic circuit.

5. The bi-directional communication bus system of claim 4, wherein said logic circuit comprises a flip-flop.

6. The bi-directional communication bus system of claim 1, wherein said interface component comprises a buffer.

7. The bi-directional communication bus system of claim 1, wherein said plurality of loopback configurations is operable to enable performance of at least one operation selected from a group consisting of calibration of a bi-directional communication bus, calibration of said first component, calibration of said second component, testing of said first component, and testing of said second component.

8. The bi-directional communication bus system of claim 1, wherein said first and second portions are further operable to implement a mission mode of operation.

9. The bi-directional communication bus system of claim 1, wherein said first portion is further operable to implement a third lane, and wherein said first lane, said second lane, and said third lane are interlaced.

10. A method comprising:

communicating signals between a first component and a second component over a first portion, wherein said first portion is operable to implement a first lane;

communicating signals between said first component and said second component over a second portion, wherein said second portion is operable to implement a second lane; and

implementing a plurality of loopback configurations for communicating signals between said first and second components one configuration at a time, wherein a first loopback configuration of said plurality of loopback configurations comprises a contemporaneous communication of signals in a first direction over said first portion and in a second direction over said second portion in a first configuration setting, wherein a second loopback configuration of said plurality of loopback configurations comprises a contemporaneous communication of signals in said second direction over said first portion and in said first direction over said second portion in a second configuration setting, wherein said second component comprises an interface component operable to couple said first and second portions, and wherein said interface component is further operable to couple said first and second portions to an auxiliary interface.

11. The method of claim 10, wherein said first component is a graphics processor, wherein said second component comprises a memory, and wherein said first and second portions comprise a memory interface.

12. The method of claim 10, wherein said first component is a memory controller, wherein said second component comprises a memory, and wherein said first and second portions comprise a memory interface.

13. The method of claim 10, wherein said interface component comprises logic circuit.

14. The method of claim 13, wherein said logic circuit comprises a flip-flop.

15. The method of claim 10, wherein said interface component comprises a buffer.

16. The method of claim 10, wherein said plurality of loopback configurations is operable to allow performance of at least one operation selected from a group consisting of calibration of a bi-directional communication bus, calibration of said first component, calibration of said second component, testing of said first component, and testing of said second component.

17. The method of claim 10, wherein said first and second portions are further operable to implement a mission mode of operation.

18. The method of claim 10, wherein said first portion is further operable to implement a third lane, and wherein said first lane, said second lane, and said third lane are interlaced.