Virtual buffer interface methods and apparatuses for use in wireless devices

• US 8,725,915 B2
• Filed: 10/01/2010
• Issued: 05/13/2014
• Est. Priority Date: 06/01/2010
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Khan, Raheel
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US12/896,622
• Publication Number:
  US 20110296120A1
• Time in Patent Office: 1,320 Days
• Field of Search: None
• US Class Current: 710/52
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a virtual buffer interface capability between a plurality of processes/engines and a memory pool.

Claims

1. A method comprising:

in response to at least one memory access request from at least one of a plurality of client processes specifying at least one virtual address associated with at least one of a plurality of virtual buffers, generating at least one physical address associated with a memory based, at least in part, on said at least one virtual address, said at least one of a plurality of virtual buffers being capable of operatively serving a plurality of client processes; and

accessing at least a portion of said memory operatively associated with said at least one physical address, said accessing comprising performing either a data packing operation as part of a write operation or a data unpacking operation as part of a read operation, said data packing and/or said data unpacking being based at least in part on a word bit width associated with said at least one of said plurality of client processes.

2. The method as recited in claim 1, wherein said memory comprises a memory pool comprising a plurality of separately controllable memory units.

3. The method as recited in claim 2, further comprising:

selectively altering a power state and/or a mode of at least one of said plurality of separately controllable memory units of said memory.

4. The method as recited in claim 3, further comprising:

determining at least one interface usage parameter associated with said at least one of said plurality of separately controllable memory units; and

selectively altering said power state and/or said mode of said at least one of said plurality of separately controllable memory units based, at least in part, on said at least one interface usage parameter.

5. The method as recited in claim 1, wherein at least two of said plurality of virtual buffers are operatively configured:

for use by at least two different client processes; and

/or

to store accessible data in at least two different word bit widths.

6. The method as recited in claim 5, wherein said at least two different word bit widths correspond to at least two different client processes.

7. The method as recited in claim 1, further comprising:

associating said at least one virtual address with at least one data parameter.

8. The method as recited in claim 7, wherein said at least one data parameter identifies at least one of:

said word bit width;

a desired bandwidth associated with said at least one of said plurality of client processes;

or

a desired data access type associated with said at least one of said plurality of client processes.

9. The method as recited in claim 8, wherein said data access type identifies either a sequential data access or a non-sequential data access.

10. The method as recited in claim 1, wherein at least one other of said plurality of virtual buffers is configured for use by a single client process.

11. The method as recited in claim 1, wherein generating said at least one physical address associated with said memory further comprises:

mapping said virtual address to a corresponding said physical address based, at least in part, on address translation information.

12. The method as recited in claim 1, further comprising, as part of said write operation, performing a read-modify-write operation.

13. The method as recited in claim 1, further comprising:

storing data in local cache memory associated with said at least one of said plurality of virtual buffers.

14. An apparatus comprising:

memory; and

a virtual buffer interface coupled to said memory and comprising;

a plurality of virtual buffers, wherein at least one of said plurality of virtual buffers is configured to provide an interface to said memory for a plurality of client processes by generating at least one physical address associated with said memory based, at least in part, on at least one virtual address as identified by at least one of said plurality of client processes, access at least a portion of said memory associated with said at least one physical address, and based, at least in part, on a word bit width associated with said at least one of said plurality of client processes perform at least one of;

a data packing operation, and/or a data unpacking operation.

15. The apparatus as recited in claim 14, wherein said memory comprises a memory pool comprising a plurality of separately controllable memory units.

16. The apparatus as recited in claim 15, wherein at least one of said plurality of separately controllable memory units has at least one selectable power state and/or operating mode.

17. The apparatus as recited in claim 15, wherein said virtual buffer interface further comprises:

an arbiter coupled to at least a portion of said plurality of virtual buffers to;

selectively alter a power state and/or mode of said one or more separately controllable memory units of said memory; and

/or

selectively alter said power state and/or mode of said one or more separately controllable memory units of said memory based, at least in part, on at least one interface usage parameter.

18. The apparatus as recited in claim 14, wherein at least two of said plurality of virtual buffers are operatively configured:

for use by at least two different client processes; and

/or

to store accessible data in at least two different word bit widths.

19. The apparatus as recited in claim 18, wherein said at least two different word bit widths correspond to at least two different client processes.

20. The apparatus as recited in claim 14, wherein said at least one virtual address is obtained via a memory access request and is associated with at least one data parameter.

21. The apparatus as recited in claim 20, wherein said at least one data parameter identifies at least one of:

said word bit width;

a desired bandwidth associated with said at least one of said plurality of client processes;

or

a desired data access type associated with said at least one of said plurality of client processes.

22. The apparatus as recited in claim 21, wherein said data access type identifies either sequential data access or non-sequential data access.

23. The apparatus as recited in claim 14, wherein at least one of said plurality of virtual buffers is configured for use by a single client process.

24. The apparatus as recited in claim 14, wherein said virtual buffer interface further comprises:

an arbiter coupled to at least a portion of said plurality of virtual buffers to establish address translation information, and wherein said at least one of said plurality of virtual buffers is further configured to map said virtual address to a corresponding said physical address based, at least in part, on said address translation information.

25. The apparatus as recited in claim 14, wherein said at least one of said plurality of virtual buffers comprises at least one of:

a reader and/or source interface;

a writer and/or sink interface;

or

a bridge interface.

26. The apparatus as recited in claim 25, wherein at least one of said writer or sink interface and/or said bridge interface to access at least a portion of at least one of said virtual buffers using a read-modify-write operation.

27. The apparatus as recited in claim 14, wherein at least one of said plurality of virtual buffers comprises a local cache memory.

28. The apparatus as recited in claim 14, wherein said virtual buffer interface further comprises:

an arbiter coupled to at least a portion of said plurality of virtual buffers, and wherein said at least one of said plurality of virtual buffers to further provide at least one interface usage parameter to said arbiter.

29. The apparatus as recited in claim 14, wherein said at least one of said plurality of client processes that is operatively coupled to at least one wireless interface.

30. The apparatus as recited in claim 29, said at least one wireless interface to support at least two air interface modes having different data storage formats.

31. An apparatus comprising:

means for obtaining at least one memory access request from at least one of a plurality of client processes said memory access request specifying at least one virtual address associated with at least one of a plurality of virtual buffers;

means for generating at least one physical address associated with a memory based, at least in part, on said at least one virtual address;

means for accessing at least a portion of said memory associated with said at least one physical address; and

at least one of;

means for performing a data packing operation as part of a write operation based, at least in part, on a word bit width associated with said at least one of said plurality of client processes; and

/or

means for performing a data unpacking operation as part of a read operation based, at least in part, on said word bit width associated with said at least one of said plurality of client processes.

32. The apparatus as recited in claim 31, wherein said memory comprises a memory pool comprising a plurality of separately controllable memory units.

33. The apparatus as recited in claim 32, further comprising:

means for selectively altering a power state and/or a mode of at least one of said plurality of separately controllable memory units of said memory.

34. The apparatus as recited in claim 33, further comprising

means for determining at least one interface usage parameter associated with said at least one of said plurality of separately controllable memory units;

and

means for selectively altering said power state and/or said mode of said at least one of said plurality of separately controllable memory units based, at least in part, on said at least one interface usage parameter.

35. The apparatus as recited in claim 31, wherein at least two of said plurality of virtual buffers are operatively configured:

for use by at least two different client processes; and

/or

to store accessible data in at least two different word bit widths.

36. The apparatus as recited in claim 35, wherein said at least two different word bit widths correspond to at least two different client processes.

37. The apparatus as recited in claim 31, further comprising:

means for associating said at least one virtual address with at least one data parameter.

38. The apparatus as recited in claim 37, wherein said at least one data parameter identifies at least one of:

said word bit width;

a desired bandwidth associated with said at least one of said plurality of client processes;

or

a desired data access type associated with said at least one of said plurality of client processes.

39. The apparatus as recited in claim 38, wherein said data access type identifies either a sequential data access or a non-sequential data access.

40. The apparatus as recited in claim 31, further comprising:

means for interfacing a single client process to said memory.

41. The apparatus as recited in claim 31, further comprising:

means for mapping said virtual address to a corresponding said physical address based, at least in part, on address translation information.

42. The apparatus as recited in claim 31, further comprising:

means for performing a read-modify-write process as part of said write operation.

43. An article comprising:

a non-transitory computer-readable medium having stored thereon computer-implementable instructions executable by at least one processing unit to;

obtain at least one memory access request from at least one of a plurality of client processes, said memory access request specifying at least one virtual address associated with at least one of said plurality of virtual buffers;

generate at least one physical address associated with a memory based, at least in part, on said at least one virtual address, said at least one of said plurality of virtual buffers being capable of operatively serving a plurality of client processes; and

initiate access of at least a portion of said memory associated with said at least one physical address, said access comprising at least one of a data packing operation that is performed as part of a write operation, or a data unpacking operation that is performed as part of a read operation, wherein said data packing and/or said data unpacking being based at least in part on a word bit width associated with said at least one of said plurality of client processes.

44. The article as recited in claim 43, wherein said memory comprises a memory pool comprising a plurality of separately controllable memory units.

45. The article as recited in claim 44, said computer-implementable instructions being further executable by said at least one processing unit to:

initiate selectively altering of a power state and/or a mode of at least one of said plurality of separately controllable memory units of said memory.

46. The article as recited in claim 45, said computer-implementable instructions being further executable by said at least one processing unit to:

obtain at least one interface usage parameter associated with said at least one of said plurality of separately controllable memory units; and

initiate selectively altering of said power state and/or said mode of said at least one of said plurality of separately controllable memory units based, at least in part, on said at least one interface usage parameter.

47. The article as recited in claim 43, wherein at least two of said plurality of virtual buffers are operatively configured:

for use by at least two different client processes; and

/or

to store accessible data in at least two different word bit widths.

48. The article as recited in claim 47, wherein said at least two different word bit widths correspond to at least two different client processes.

49. The article as recited in claim 43, said computer-implementable instructions being further executable by said at least one processing unit to:

associate said at least one virtual address with at least one data parameter.

50. The article as recited in claim 49, wherein said at least one data parameter identifies at least one of:

said word bit width;

a desired bandwidth associated with said at least one of said plurality of client processes;

or

a desired data access type associated with said at least one of said plurality of client processes.

51. The article as recited in claim 50, wherein said data access type identifies either a sequential data access or a non-sequential data access.

52. The article as recited in claim 43, wherein at least one other of said plurality of virtual buffers is configured for use by a single client process.

53. The article as recited in claim 43, said computer-implementable instructions being further executable by said at least one processing unit to:

map said virtual address to a corresponding said physical address based, at least in part, on address translation information.

54. The article as recited in claim 43, wherein, as part of said write operation, a read-modify-write operation is performed.