Reducing access contention in flash-based memory systems

• US 8,725,957 B2
• Filed: 08/01/2012
• Issued: 05/13/2014
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Eleftheriou, Evangelos S., Haas, Robert, Mueller, Peter, Pletka, Roman A.
• Primary Examiner(s): DOAN, DUC T
• Application Number:
  US13/563,947
• Publication Number:
  US 20120297128A1
• Time in Patent Office: 650 Days
• Field of Search: None
• US Class Current: 711/150
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.

Claims

1. A method for reducing access contention in a memory chip having a channel and memory blocks, the method comprising:

setting a write state and a write queue head within the channel, the channel including chip stripes;

setting the write queue head to a first free page in the channel;

allocating write requests according to a write allocation scheduler for the channel;

generating a page write;

in response to the page write, incrementing the write queue head; and

setting an on-line state in the channel,

wherein the memory chip is not in an erase state during the write state of one or more of the chip stripes.

2. The method as claimed in claim 1 further comprising triggering garbage collection.

3. The method as claimed in claim 2 wherein garbage collection is triggered in response to a change to the write state in the channel.

4. The method as claimed in claim 2 wherein garbage collection is triggered in response to reaching a predetermined threshold in the channel.

5. The method as claimed in claim 2 wherein garbage collection is triggered in response to a memory block becoming full.

6. The method as claimed in claim 2 wherein garbage collection comprises:

setting a cleaning state in the channel;

reading page meta-data and LBA-to-PBA mapping information;

in response to a page being valid;

reading full page data;

obtaining a target location for the page;

writing page data to new location;

setting an erase state in the channel

erasing all blocks within the channel; and

setting a free state in the channel.

7. A computer program product for reducing access contention in a memory chip having a channel and a memory blocks, the computer program product including instructions for causing a computer to implement a method, the method comprising:

setting a write state and a write queue head within the channel, the channel including chip stripes;

setting the write queue head to a first free page in the channel;

allocating write requests according to a write allocation scheduler for the channel

generating a page write;

in response to the page write, incrementing the write queue head; and

setting an on-line state in the channel,

wherein the memory chip is not in an erase state during the write state of one or more of the chip stripes.

8. The computer program product as claimed in claim 7 wherein the method further comprises triggering garbage collection.

9. The computer program product as claimed in claim 8 wherein garbage collection is triggered in response to a last free chip stripe changed to the write state in the channel.

10. The computer program product as claimed in claim 8 wherein garbage collection is triggered in response to reaching a predetermined threshold in the channel.

11. The computer program product as claimed in claim 8 wherein garbage collection is triggered in response to a memory block becoming full.

12. The computer program product as claimed in claim 8 wherein garbage collection comprises:

setting a cleaning state in the channel;

reading page meta-data and LBA-to-PBA mapping information;

in response to a page being valid;

reading full page data;

obtaining a target location for the page;

writing page data to new location;

setting an erase state in the channel

erasing all blocks within the channel; and

setting a free state in the channel.

13. A memory system, comprising:

a channel having a write allocation scheduler, the channel supporting a free state, a write state, an online state and an erase state, the channel including chip stripes;

wherein the channel is configured to support changing set the free state to the write state to allocate write requests, and is further configured to support changing the write state to the on-line state,

wherein the memory system is not in an erase state during the write state of one or more of the chip stripes.

14. The memory system as claimed in claim 13 further comprising a write queue head disposed in the channel,

wherein the system is configured for:

setting the write queue head to a first free page in a chip belonging to the channel;

allocating write requests according to the write allocation scheduler;

generating a page write; and

in response to the page write, incrementing the write queue head; and

setting an on-line state in the channel.

15. The memory system as claimed in claim 14 wherein the system is further configured for triggering garbage collection is in response to a change to the write state in the channel.

16. The memory system as claimed in claim 15 wherein garbage collection is triggered when a memory block is full and a predetermined threshold of free blocks on the memory system is reached.

17. The memory system as claimed in claim 15 wherein garbage collection comprises:

setting a cleaning state in the channel;

reading page meta-data and LBA-to-PBA mapping information;

in response to a page being valid;

reading full page data;

obtaining a target location for the page;

writing page data to new location;

setting an erase state in the channel

erasing all blocks within the channel; and

setting a free state in the channel.