Progressive memory initialization with waitpoints
First Claim
1. A method comprising:
- initializing a counter value of a hardware counter in response to an initialization stimulus;
iteratively adjusting the counter value and storing an initialization value to a memory location of a memory array using a memory address that is based on the counter value;
generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting the counter value and storing the initialization value;
suspending an execution of a software program by a data processor prior to the generation of the interrupt request; and
resuming the execution of the software program in response to the generation of the interrupt request.
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Accused Products
Abstract
A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.
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Citations
20 Claims
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1. A method comprising:
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initializing a counter value of a hardware counter in response to an initialization stimulus; iteratively adjusting the counter value and storing an initialization value to a memory location of a memory array using a memory address that is based on the counter value; generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting the counter value and storing the initialization value; suspending an execution of a software program by a data processor prior to the generation of the interrupt request; and resuming the execution of the software program in response to the generation of the interrupt request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a memory device comprising; a memory array comprising a plurality of memory locations; and an initialization module comprising; a counter; a first register configured to store a first waitpoint value; write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter; and interrupt logic configured to generate a first interrupt request based on a comparison of the counter value of the counter to the first waitpoint value concurrent with iteratively adjusting the counter value and writing the initialization value; and a processor coupled to the memory device and configured to receive the first interrupt request and to resume a suspended execution of a software program in response to receiving the first interrupt request. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a processor; interrupt logic configured to generate an interrupt request based on a comparison of a counter value of a hardware counter to a waitpoint value stored in a register concurrent with iteratively adjusting the counter value and writing an initialization value to a memory of a memory array; and a computer-readable medium embodying a set of executable instructions, the set of executable instructions including at least one executable instruction configured to manipulate the processor to; store a waitpoint value at the register; suspend an execution of the set of executable instructions to wait for an interrupt request from the interrupt logic based on the waitpoint value; and resume the execution of the set of executable instructions in response to the interrupt request from the interrupt logic. - View Dependent Claims (18, 19, 20)
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Specification