System on chip, devices having the same, and method for power control of the SOC
First Claim
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1. An integrated circuit device, comprising:
- a plurality of power domain blocks, comprising a core power domain block; and
a power control circuit that is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block, the power control circuit comprising a plurality of power clusters corresponding to the plurality of power domain blocks, respectively;
wherein the plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block; and
wherein at least two of the power clusters control one of power on/off, clock on/off, data retention and isolation of the corresponding power domain block respectively.
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Abstract
Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.
30 Citations
23 Claims
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1. An integrated circuit device, comprising:
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a plurality of power domain blocks, comprising a core power domain block; and a power control circuit that is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block, the power control circuit comprising a plurality of power clusters corresponding to the plurality of power domain blocks, respectively; wherein the plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block; and wherein at least two of the power clusters control one of power on/off, clock on/off, data retention and isolation of the corresponding power domain block respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 16)
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11. A System on Chip (SoC) comprising:
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a plurality of power domains each including a plurality of intellectual properties (IPs); a power control unit including a plurality of finite state machines each controlling a power state and an operation state of each of the plurality of power domains independently according to register values set in a register embodied therein; and a central sequencer determining an activation sequence or whether to activate each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register included therein; wherein each of the plurality of finite state machines comprises; a plurality of sub-finite state machines each controlling the power state and the operation state independently; and a main state machine determining an activation sequence or whether to activate each of the plurality of sub-finite state machines according to the register values set therein. - View Dependent Claims (12, 13, 14, 15, 17, 18, 19, 20)
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21. A System on Chip (SoC) comprising:
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a plurality of power domains each including a plurality of intellectual properties (IPs); a power control unit each including a plurality of finite state machines controlling a power state and an operation state of each of the plurality of power domains independently according to register values set in a register embodied therein; a central sequencer determining an activation sequence or whether to activate each of the plurality of finite state machines according to at least one central configuration register value set in a central configuration register included therein; and a reset sequencer controlling each reset operation of a plurality of finite state machines performing a reset function among the plurality of finite state machines.
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22. A System on Chip (SoC) comprising:
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a plurality of power domains each including a plurality of intellectual properties (IPs); and a power control unit including a plurality of finite state machines (FSMs) embodied hierarchically, wherein an activation sequence or whether to activate each of children FSMs among the plurality of FSMs is determined according to first register values set in a parent FSM where each of the children FSMs belongs; wherein an activation sequence or whether to activate each of grandchildren FSMs belonging to each of the children FSMs is determined according to second register values set in each of the children FSMs, wherein each of the grandchild FSMs controls independently a power state and an operation state of each of the plurality of IPs included in each of the plurality of power domains; and wherein at least two of the finite state machines embodied hierarchically in the power control unit controls one of power on/off, clock on/off, data retention, and isolation of one of the plurality of power domains respectively. - View Dependent Claims (23)
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Specification