Power management of components having clock processing circuits

• US 8,726,057 B2
• Filed: 06/04/2013
• Issued: 05/13/2014
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Allen, Daniel J.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US13/909,443
• Publication Number:
  US 20130262897A1
• Time in Patent Office: 343 Days
• Field of Search: 713/300, 713/320, 713/322, 713/340, 713/500, 713/501, 713/600, 327/100, 327/105, 327/106
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms.

Claims

1. A method comprising:

generating a plurality of clock signals each of which is for supply to a corresponding one of a plurality of clock processing circuits, wherein generating comprises generating digital period values each of which describes a period of a corresponding one of the plurality of clock signals at a cycle of the respective clock signal, wherein each of the plurality of clock signals is produced by a digital waveform synthesizer that is capable of changing a frequency of each clock signal every clock cycle in response to a digital period value received as an input thereto; and

changing a frequency of each of the plurality of clock signals, by changing the digital period values supplied as input to the digital waveform synthesizer in order to change the frequency of each of the plurality of clock signals, according to at least one operating characteristic of a corresponding clock processing circuit so as to maintain acceptable operating parameters of the respective clock processing circuit during a change in frequency of the corresponding clock signal, wherein changing comprises changing the frequency of a particular clock signal supplied to a corresponding particular clock processing circuit depending on an operating condition of another clock processing circuit.

2. The method of claim 1, wherein changing comprises initiating the change of the frequency of the particular clock signal so that a processed clock signal produced by the corresponding particular clock processing circuit completes a frequency change before or after changing a frequency of a processed clock signal produced by said other clock processing circuit.

3. The method of claim 1, wherein changing the frequency of the particular clock signal supplied to the particular clock processing circuit in order to manage power consumption of the particular clock processing circuit.

4. The method of claim 3, wherein changing comprises changing the frequency of the particular clock signal so as to reduce a time interval required for a transition of the particular processed clock signal produced by the particular clock processing circuit from a first frequency to a second frequency.

5. The method of claim 3, wherein changing comprises changing the frequency of the particular clock signal to each of multiple different frequencies thereby invoking a change in frequency of the particular processed clock signal to each of the multiple different frequencies, each frequency of the particular processed clock signal associated with a different power consumption level.

6. The method of claim 3, wherein changing comprises changing the frequency of the particular clock signal supplied to the particular clock processing circuit based on at least one operating condition of a power supply.

7. The method of claim 6, and further comprising monitoring the at least one operating condition of the power supply.

8. The method of claim 7, wherein monitoring comprises monitoring at least one of:

a switching rate with respect to bypass capacitors of the power supply and a voltage level of the power supply.

9. The method of claim 6, wherein changing further comprises changing the frequency of the particular clock signal supplied to the power supply.

10. A method comprising:

generating a plurality of clock signals each of which is for supply to a corresponding one of a plurality of clock processing circuits, wherein generating comprises generating digital period values each of which describes a period of a particular clock signal at a cycle of the particular clock signal supplied as input to a particular clock processing circuit, wherein the particular clock signal is produced by a digital waveform synthesizer that is capable of changing a frequency of the particular clock signal every clock cycle in response to a digital period value received as an input thereto;

changing a frequency of each of the plurality of clock signals according to at least one operating characteristic of a corresponding clock processing circuit so as to maintain acceptable operating parameters of the respective clock processing circuit during a change in frequency of the corresponding clock signal, and wherein changing comprises;

changing the digital period values supplied as input to the digital waveform synthesizer in order to reduce the time interval required for the transition of the particular clock signal from a first frequency to a second frequency and in order to manage power consumption of the particular clock processing circuit to which the particular clock signal is supplied.

11. A system comprising:

a clock circuit that generates a plurality of clock signals each of which is supplied to a corresponding one of a plurality of clock processing circuits, wherein the clock circuit comprises a digital waveform synthesizer circuit that generates the plurality of clock signals based on digital period values supplied as input to the digital waveform synthesizer circuit, wherein each digital period value describes a period of a corresponding clock signal at a cycle of the corresponding clock signal, and wherein the digital waveform synthesizer circuit is capable of changing the frequency of each clock signal every clock cycle in response to corresponding digital period values received as input thereto; and

a control circuit that controls the clock circuit to change a frequency of each of the plurality of clock signals, by changing the digital period values supplied as input to the digital waveform synthesizer in order to change the frequency of each of the plurality of clock signals, according to at least one operating characteristic of the corresponding clock processing circuit so as to maintain acceptable operating parameters of the respective clock processing circuit during a change in frequency made thereto, wherein the control circuit is configured to change the frequency of a particular clock signal supplied to a corresponding particular clock processing circuit depending on an operating condition of another clock processing circuit.

12. The system of claim 11, wherein the control circuit is configured to change the frequency of the particular clock signal in order to manage power consumption of the particular clock processing circuit.

13. The system of claim 12, wherein the control circuit is configured to change the frequency of the particular clock signal so as to reduce a time interval required for a transition of the particular processed clock signal by the particular clock processing circuit from a first frequency to a second frequency.

14. The system of claim 12, wherein the control circuit is configured to change the frequency of the particular clock signal to each of multiple different frequencies thereby invoking a change in frequency of the particular processed clock signal to each of the multiple different frequencies, each frequency of the particular processed clock signal associated with a different power consumption level.

15. The system of claim 12, wherein the control circuit is configured to change the frequency of the particular clock signal supplied to the particular clock processing circuit based on at least one operation condition of a power supply.

16. The system of claim 15, wherein the control circuit is configured to change the frequency of the particular clock signal supplied to the power supply.

17. The system of claim 15, wherein the control circuit is configured to monitor at least one of:

a switching rate with respect to bypass capacitors of the power supply and a voltage level of the power supply.

18. A system comprising:

a clock circuit that generates a plurality of clock signals each of which is supplied to a corresponding one of a plurality of clock processing circuits, wherein the clock circuit comprises a digital waveform synthesizer circuit that generates a particular clock signal supplied as input to a particular clock processing circuit based on digital period values supplied as input to the digital waveform synthesizer circuit, wherein each digital period value describes a period of the particular clock signal at a cycle of the clock signal, and wherein the digital waveform synthesizer circuit is capable of changing the frequency of the particular clock signal every clock cycle in response to corresponding digital period values received as input thereto; and

a control circuit that controls the clock circuit to change a frequency of each of the plurality of clock signals according to at least one operating characteristic of the corresponding clock processing circuit so as to maintain acceptable operating parameters of the respective clock processing circuit during a change in frequency made thereto, wherein the control circuit is configured to change the frequency of the particular clock signal in order to manage power consumption of the particular clock processing circuit, and to supply digital period values to the digital waveform synthesizer circuit in order to change the frequency of the particular clock signal in order to reduce the time interval required for the transition of the particular clock signal from a first frequency to a second frequency.