Selective per-cycle masking of scan chains for system level test
First Claim
Patent Images
1. A circuit, comprising:
- a memory;
a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator;
a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals;
a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and
one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals.
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Abstract
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
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Citations
25 Claims
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1. A circuit, comprising:
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a memory; a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator; a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals; a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. One or more non-transitory computer-readable storage media storing design data describing a circuit, the circuit comprising:
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a memory; a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator; a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals; a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals. - View Dependent Claims (11, 12, 13)
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14. A method, comprising:
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receiving circuit design information representative of a circuit-under-test; and generating selection logic for testing the circuit-under-test, the selection logic comprising; a memory; a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator; a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals; a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals. - View Dependent Claims (15, 16)
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17. One or more non-transitory computer-readable storage media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
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receiving circuit design information representative of a circuit-under-test; and generating selection logic for testing the circuit-under-test, the selection logic comprising; a memory; a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator; a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals; a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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Specification