Method and apparatus for decomposing functions in a configurable IC

• US 8,726,213 B2
• Filed: 03/30/2009
• Issued: 05/13/2014
• Est. Priority Date: 03/15/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Caldwell, Andrew, Schmit, Herman, Teig, Steven
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US12/414,660
• Publication Number:
  US 20090243651A1
• Time in Patent Office: 1,870 Days
• Field of Search: 716/101, 716/116, 716/126
• US Class Current: 716/116
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Claims

1. An integrated circuit (“

IC”

) comprising;

a configurable logic circuit with n input terminals for configurably performing a set of functions, wherein n is a number greater than 1 and each of the n input terminals receives a user-design signal; and

a set of input select interconnect circuits for providing the user design signals to the input terminals of the configurable logic circuit, each input select interconnect circuit having a set of select terminals that is controlled by a first set of configuration data, wherein;

(i) when the first set of configuration data has a first value, the set of select terminals receives a second set of configuration data such that the input select interconnect circuit selects one user design signal to route to an input terminal of the configurable logic circuit; and

(ii) when the first set of configuration data has a second value, at least one select terminal in the set of select terminals receives a user design signal that causes the input select interconnect circuit to perform a particular m-input logic function with the configurable logic circuit, wherein m is a number greater than n.

2. The IC of claim 1, wherein the input select interconnect circuit receives (m-n) user design signals along (m-n) select terminals of the input select interconnect circuit.

3. The IC of claim 1, wherein the set of input select interconnect circuits are hybrid interconnect/logic circuits.

4. The IC of claim 1, wherein each input select interconnect circuit operates as an interconnect circuit when it receives only configuration data at its select terminals and operates as a logic circuit when it receives at least one user design signal at one of its select terminals.

5. The IC of claim 1, wherein at least one input select interconnect circuit in the set of input select interconnect circuits has a permanently inverting input.

6. The IC of claim 1, wherein the configurable logic circuit and the set of input select interconnect circuits are used to decompose the particular m-input function into a set of functions, each with less than m inputs.

7. The IC of claim 1, wherein the input select interconnect circuit uses a first user design signal to select a second user design signal to route to an input terminal of the configurable logic circuit when the first set of configuration data has the second value.

8. An electronic device comprising:

a memory for storing sets of configuration data; and

an integrated circuit (“

IC”

) comprising;

a configurable logic circuit with n-input terminals for configurably performing a set of functions based on a set of configuration data for the configurable logic circuit, wherein n is a number greater than 1 and each of the n input terminals receives a user design signal; and

a set of input select interconnect circuits for providing the user design signals to the input terminals of the configurable logic circuit, each input select interconnect circuit having a set of select terminals, wherein;

(i) when the sets of select terminals of the set of input select interconnect circuits configurably receive a first set of signals that comprises only configuration data, each input select interconnect circuit selects a user design signal to route to an input terminal of the configurable logic circuit;

(ii) when the sets of select terminals of the set of input select interconnect circuits configurably receive a second set of signals that comprises at least one user design signal, at least a subset of the input select interconnect circuits performs a particular m-input logic function with the configurable logic circuit, wherein m is a number greater than n.

9. The electronic device of claim 8, wherein each input select interconnect circuit has a set of input terminals and a set of output terminals, wherein the set of input select interconnect circuits receives (m-n) user design signals along (m-n) select terminals.

10. The electronic device of claim 8, wherein the set of input select interconnect circuits are hybrid interconnect/logic circuits.

11. The electronic device of claim 10, wherein a hybrid interconnect/logic circuit operates as an interconnect circuit when it receives only configuration data at its select terminals and operates as a logic circuit when it receives at least one user design signal at one of its select terminals.

12. The electronic device of claim 8, wherein at least one input select interconnect circuit in the set of input select interconnect circuits has a permanently inverting input.

13. The electronic device of claim 8, wherein the configurable logic circuit and the set of input select interconnect circuits are used to decompose particular the m-input function into a set of functions, each with less than m inputs.

14. The electronic device of claim 8, wherein each of the subset of the input select interconnect circuits uses a first user design signal to select a second user design signal to route to an input terminal of the configurable logic circuit when the sets of select terminals of the set of input select interconnect circuits configurably receive the second set of signals.

15. An integrated circuit (“

IC”

) comprising;

a configurable logic circuit with n input terminals for configurably performing a set of functions, wherein n is a number greater than 1 and each of the n input terminals receives a user-design signal; and

a set of input select interconnect circuits for providing the user design signals to the input terminals of the configurable logic circuit, each input select interconnect circuit having a set of select terminals that configurably receive signals based on a first set of configuration data, wherein;

(i) when the first set of configuration data has a first value, the set of select terminals receives a second set of configuration data such that the input select interconnect circuit selects one user design signal to route to an input terminal of the configurable logic circuit; and

(ii) when the first set of configuration data has a second value, at least one select terminal in the set of select terminals receives a user design signal that causes the input select interconnect circuit to perform a particular m-input logic function with the configurable logic circuit, wherein m is a number greater than n.

16. The IC of claim 15, wherein the input select interconnect circuit uses a first user design signal to select a second user design signal to route to an input terminal of the configurable logic circuit when the first set of configuration data has the second value.

17. The IC of claim 15, wherein the set of input select interconnect circuits are hybrid interconnect/logic circuits.

18. The IC of claim 15, wherein each input select interconnect circuit operates as an interconnect circuit when it receives only configuration data at its select terminals and operates as a logic circuit when it receives at least one user design signal at one of its select terminals.

19. The IC of claim 15, wherein at least one input select interconnect circuit in the set of input select interconnect circuits has a permanently inverting input.

20. The IC of claim 15, wherein the configurable logic circuit and the set of input select interconnect circuits are used to decompose the particular m-input function into a set of functions, each with less than m inputs.