Vertical thermoelectric structures

• US 8,728,846 B2
• Filed: 08/20/2009
• Issued: 05/20/2014
• Est. Priority Date: 08/20/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Male, Barry Jon, Hower, Philip L.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US12/544,548
• Publication Number:
  US 20100044704A1
• Time in Patent Office: 1,734 Days
• Field of Search: 438/54, 257/773, 257/E29.347, 257/E21.532
• US Class Current: 438/54
• CPC Class Codes: H01L 23/38 Cooling arrangements using the Peltier effect
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10N 10/13 characterised by the heat-exchanging means at the junction
• CPC Class Codes: H10N 10/17 characterised by the structure or configuration of the cell or thermocouple forming the device
• CPC Class Codes: H10N 10/855 comprising compounds containing boron, carbon, oxygen or nitrogen
• CPC Class Codes: H10N 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00

Abstract

A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Claims

1. A method of forming an integrated circuit, comprising the steps of:

forming a first metal thermal terminal at a top surface of said integrated circuit;

forming a second metal thermal terminal at said top surface of said integrated circuit;

forming a first vertical thermally conductive conduit in said integrated circuit, by a process further comprising the steps of;

forming a first horizontal metal interconnect element which makes contact to a bottom surface of said first metal thermal terminal;

forming a first plurality of vertical metal interconnect elements which makes thermal contact to a bottom surface of said first plurality of horizontal metal interconnect elements;

forming a second horizontal metal interconnect element which makes thermal contact to a bottom surface of said first plurality of vertical metal interconnect elements; and

forming a second plurality of vertical metal interconnect elements which makes thermal contact to a bottom surface of said second plurality of horizontal metal interconnect elements;

forming a second vertical thermally conductive conduit in said integrated circuit, by a process further comprising the steps of;

forming a third horizontal metal interconnect element which makes contact to a bottom surface of said second metal thermal terminal;

forming a third plurality of vertical metal interconnect elements which makes thermal contact to a bottom surface of said third plurality of horizontal metal interconnect elements;

forming a fourth horizontal metal interconnect element which makes thermal contact to a bottom surface of said third plurality of vertical metal interconnect elements; and

forming a fourth plurality of vertical metal interconnect elements which makes thermal contact to a bottom surface of said fourth plurality of horizontal metal interconnect elements;

forming a first lateral thermoelectric element in said integrated circuit, such that a first end of said first lateral thermoelectric element is thermally connected to a bottom surface of said second plurality of vertical metal interconnect elements and a second end of said first lateral thermoelectric element is thermally connected to a silicon substrate of said integrated circuit;

forming a second lateral thermoelectric element in said integrated circuit, such that a first end of said second lateral thermoelectric element is thermally connected to a bottom surface of said fourth plurality of vertical metal interconnect elements and a second end of said second lateral thermoelectric element is thermally connected to said silicon substrate of said integrated circuit;

forming a first region of silicon dioxide thicker than 250 nanometers in said silicon substrate under said first lateral thermoelectric element;

forming a second region of silicon dioxide thicker than 250 nanometers in said silicon substrate under said second lateral thermoelectric element;

forming a first electrically conducting element between an electrically negative end of said first lateral thermoelectric element and an electrically positive end of said second lateral thermoelectric element;

forming a second electrically conducting element between an electrically positive end of said first lateral thermoelectric element and a first transistor contained in said integrated circuit; and

forming a third electrically conducting element between an electrically negative end of said second lateral thermoelectric element and a second transistor contained in said integrated circuit.

2. The method of claim 1, in which:

said first lateral thermoelectric element is comprised of polycrystalline silicon; and

said second lateral thermoelectric element is comprised of polycrystalline silicon.

3. The method of claim 2, further comprising the steps of:

forming a first electrically insulating layer less than 20 nanometers thick between said first plurality of vertical metal interconnect elements and said second plurality of horizontal metal interconnect elements; and

forming a second electrically insulating layer less than 20 nanometers thick between said third plurality of vertical metal interconnect elements and said fourth plurality of horizontal metal interconnect elements.

4. The method of claim 2, further comprising the steps of;

forming a first thermally insulating region under said first region of silicon dioxide; and

forming a second thermally insulating region under said second region of silicon dioxide.

5. The method of claim 2, in which:

said silicon substrate is p-type; and

further comprising the steps of

forming a first n-type isolation well in said silicon substrate under said second end of said first lateral thermoelectric element, and electrically connected to said second end of said first lateral thermoelectric element; and

forming a second n-type isolation well in said silicon substrate under said second end of said second lateral thermoelectric element, and electrically connected to said second end of said second lateral thermoelectric element.

6. The method of claim 2, further comprising the steps of:

forming a dielectric layer less than 20 nanometers thick on a top surface of said silicon substrate, such that said second end of said first lateral thermoelectric element contacts a top surface of said dielectric layer and said second end of said second lateral thermoelectric element contacts said top surface of said dielectric layer.