Method for producing contact openings in a semiconductor body and self-aligned contact structures on a semiconductor body

• US 8,728,891 B2
• Filed: 07/27/2012
• Issued: 05/20/2014
• Est. Priority Date: 09/21/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hofer, Heimo, Poelzl, Martin
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/560,091
• Publication Number:
  US 20120315759A1
• Time in Patent Office: 662 Days
• Field of Search: 438/268, 438/270, 438/272, 438/299, 438/424, 438/427, 438/430, 438/435, 438/589, 438/597, 438/620, 438/621
• US Class Current: 438/270
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.

Claims

1. A method for producing contact openings in a semiconductor body, the method comprising:

forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface, adjacent ones of the self-aligned structures having spaced apart sidewalls which face each other;

forming a spacer layer on the sidewalls of the self-aligned structures; and

forming openings in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures so that each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer.

2. The method according to claim 1, wherein forming the self-aligned structures on the main surface of the semiconductor body comprises:

forming a plurality of trenches extending from the main surface of the semiconductor body into the semiconductor body;

forming a first layer on the main surface and in the trenches, the first layer having recessed regions over the trenches;

forming a second layer on the first layer, the second layer filling the recessed regions of the first layer; and

forming openings in the first and second layers which extend to the main surface over island regions of the semiconductor body between adjacent ones of the trenches.

3. The method according to claim 2, wherein the first layer is formed by HDP deposition.

4. The method according to claim 2, wherein the second layer comprises carbon.

5. The method according to claim 1, wherein the spacer layer is formed by TEOS deposition.

6. The method according to claim 1, wherein the spacer layer comprises carbon.

7. The method according to claim 1, wherein the sidewalls of the self-aligned structures are tapered.

8. The method according to claim 1, further determining the thickness of the spacer layer based on a predetermined width for the openings formed in the semiconductor body between adjacent ones of the self-aligned structures.

9. The method according to claim 1, further comprising:

measuring a distance between adjacent ones of the self-aligned structures prior to formation of the spacer layer; and

determining the thickness of the spacer layer based on the measuring distance.

10. The method according to claim 9, wherein the distance between adjacent ones of the self-aligned structures is measured by scanning electron microscopy.

11. The method according to claim 9, wherein the semiconductor body is part of a semiconductor wafer and a plurality of distances between adjacent self-aligned structures are measured at different points on the wafer prior to formation of the spacer layer.

12. The method according to claim 11, further comprising:

calculating a mean value for the plurality of distance measurements; and

determining the thickness of the spacer layer based on the calculated mean value.

13. The method according to claim 12, wherein the thickness of the spacer layer corresponds to the difference between the calculated mean value and a target value for the distance between adjacent ones of the self-aligned structures.

14. A method for producing self-aligned contact structures on a semiconductor body, the method comprising:

forming a plurality of trenches extending from a main surface of a semiconductor body into the semiconductor body;

forming a conductive plate in a lower part of the trenches and insulated from the semiconductor body;

forming a first material on the main surface and on the conductive plates in the trenches, the first material having recessed regions over the trenches;

filling the recessed regions of the first material with a second material;

forming openings in the first material which extend to the main surface over island regions of the semiconductor body between adjacent ones of the trenches to form a plurality of spaced apart self-aligned structures including the second material in the recessed regions of the first material;

forming grooves in the semiconductor body between adjacent ones of the self-aligned structures; and

filling the grooves and open gaps between adjacent ones of the self-aligned structures with a material having a different etch selectivity than the first and second materials.

15. The method according to claim 14, wherein the first material is formed by HDP deposition.

16. The method according to claim 14, wherein the second material comprises carbon.

17. The method according to claim 14, further comprising removing the self-aligned structures selective to the material filling the grooves and the open gaps.

18. The method according to claim 17, further comprising forming gate conductors in an upper part of the trenches, the gate conductors insulated from the semiconductor body and the field plates.

19. The method according to claim 17, further comprising forming a spacer layer on the sidewalls of the self-aligned structures prior to forming the grooves in the semiconductor body, and wherein the grooves are formed in the semiconductor body by forming openings in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures so that each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer.

20. The method according to claim 14, wherein the material filling the grooves and the open gaps comprises nitride.