Systems and methods for producing flat surfaces in interconnect structures

• US 8,728,934 B2
• Filed: 06/24/2011
• Issued: 05/20/2014
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Uzoh, Cyprian, Oganesian, Vage, Mohammed, Ilyas
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/168,839
• Publication Number:
  US 20120326326A1
• Time in Patent Office: 1,061 Days
• Field of Search: 257/774, 257/E23.067, 257/E21.584, 438/642, 438/643, 438/618, 438/597, 438/584, 438/626, 438/629, 438/627, 438/692, 438/E21.583
• US Class Current: 438/643
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32125 by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Claims

1. A method of forming a semiconductor interconnect structure, comprising:

forming a cavity in a substrate;

depositing a barrier layer on the cavity and on a first surface of the substrate;

depositing a conductor on the barrier layer and inside the cavity;

depositing a conductive sacrificial layer on the conductor; and

removing portions of the conductive sacrificial layer, the conductor, and the barrier layer from the first surface by process including polishing until the conductor inside the cavity is angled greater than zero with respect to the first surface of the substrate,

wherein a polishing rate of the conductive sacrificial layer is less than a polishing rate of the conductor.

2. The method of claim 1 wherein the removing step comprises removing portions of the conductive sacrificial layer, the conductor, and the barrier layer until the conductor inside the cavity comprises a substantially convex surface that extends above the first surface of the substrate.

3. The method of claim 1 wherein the conductor comprises copper.

4. The method of claim 1 wherein the removing step comprises a chemical mechanical polishing process.

5. The method of claim 1 wherein the removing step comprises an electro-chemical-mechanical polishing process.

6. The method of claim 1 wherein the depositing a conductive sacrificial layer step further comprises electrolessly depositing a conductive sacrificial layer on the conductor.

7. The method of claim 1 wherein a corrosion rate of the conductive sacrificial layer is less than a corrosion rate of the conductor.

8. The method of claim 1 wherein the conductive sacrificial layer comprises a material selected from the group of Ni, Ni alloys, NiP, NiB, NiWB, NiCoP, NiMoP, NiGa nickel-tungsten, cobalt alloys, copper-tungsten, CoP, CoWP, and CMoP.

9. The method of claim 1 wherein the depositing a conductive sacrificial layer step further comprises depositing a conductive sacrificial layer having a thickness ranging from approximately 3 nm to 300 nm on the conductor.

10. The method of claim 1 wherein the depositing a conductive sacrificial layer step further comprises depositing a conductive sacrificial layer having a thickness ranging from approximately 5 nm to 50 nm on the conductor.

11. The method of claim 1 wherein the conductive sacrificial layer comprises a conformal layer.

12. The method of claim 1 wherein the conductive sacrificial layer comprises an electroplated metal.

13. A method of forming a semiconductor device, comprising:

depositing a barrier layer on a substrate comprising at least one cavity;

depositing a conductor on the barrier layer to overfill the at least one cavity;

depositing a conductive sacrificial layer on the conductor; and

removing the conductive sacrificial layer, the conductor, and the barrier layer from portions of the substrate adjacent to the at least one cavity by process including polishing until the conductor inside the cavity is angled greater than zero with respect to a surface of the substrate, and to form an interconnect structure, wherein a polishing rate of the conductive sacrificial layer is less than a polishing rate of the conductor.

14. The method of claim 13 wherein the surface is a first surface of the substrate and the interconnect structure comprises a top surface that angles upwards from the first surface of the substrate.

15. The method of claim 13 wherein the interconnect structure comprises a damascene structure.

16. The method of claim 13 wherein the interconnect structure comprises a through-silicon via structure.

17. The method of claim 13 wherein the removing the conductive sacrificial layer step further comprises removing the conductive sacrificial layer, the conductor, and the barrier layer from portions of the substrate adjacent to the at least one cavity until the conductor within the interconnect structure forms a substantially convex surface.

18. A method of forming a semiconductor interconnect structure, comprising:

forming a cavity in a substrate;

depositing a barrier layer on the cavity and on a first surface of the substrate;

depositing a conductor on the barrier layer and inside the cavity;

depositing a conductive sacrificial layer on the conductor; and

removing portions of the conductive sacrificial layer, the conductor, and the barrier layer from the first surface by a process including corrosion, until the conductor inside the cavity is angled greater than zero with respect to the first surface of the substrate, wherein a corrosion rate of the conductive sacrificial layer is less than a corrosion rate of the conductor.

19. A method of forming a semiconductor interconnect structure, comprising:

forming a cavity in a substrate;

depositing a barrier layer on the cavity and on a first surface of the substrate;

depositing a conductor on the barrier layer and inside the cavity;

depositing a conductive sacrificial layer on the conductor; and

removing portions of the conductive sacrificial layer, the conductor, and the barrier layer from the first surface until the conductor inside the cavity is angled greater than zero with respect to the first surface of the substrate.

20. The method of claim 19, wherein a corrosion rate of the conductive sacrificial layer is less than a corrosion rate of the conductor.

21. The method of claim 19, wherein a polishing rate of the conductive sacrificial layer is less than a polishing rate of the conductor.

22. The method of claim 19 wherein the depositing a conductive sacrificial layer step further comprises electrolessly depositing a conductive sacrificial layer on the conductor.

23. The method of claim 19, wherein the removing is performed until the conductor inside the cavity comprises a substantially convex surface that extends above the first surface of the substrate.